Cross-Process Queue for Single-Computer Data Transfer

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Solution Overview

Problem

Traditional computing environments face challenges in transferring data between multiple processes due to each process having its own distinct memory address space, making data transfers across processes infeasible.

Innovation Solution

Implementing a cross-process queue with in-memory cell indices and synchronization data structures to manage data transfers between operating system processes, regulating access based on available cell and channel counts, and enabling data conversion between different computer languages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If data transfer is implemented between processes with distinct memory address spaces, then data transfer capability between processes is achieved, but system complexity increases due to the need for cross-process communication mechanisms

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a shared memory region as an intermediary between processes with distinct memory address spaces. This shared memory acts as a mediator that enables data transfer without requiring direct access between processes, thus achieving data transfer capability while managing system complexity through a standardized communication interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the memory address space by creating distinct virtual memory spaces for each process while introducing a separate shared memory region. This segmentation allows processes to maintain their individual memory spaces for security and isolation while enabling controlled data transfer through the shared region, balancing versatility and complexity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If synchronization mechanisms are added to regulate access to shared memory, then data consistency is improved, but operation overhead increases due to pause and wait operations

Engineering Contradiction:
Improvedata consistencyVSAvoidoperation overhead
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent implements synchronization mechanisms that provide feedback about the state of shared memory cells to processes. By monitoring and communicating the availability status of memory cells, the system ensures data consistency while allowing processes to make informed decisions about when to proceed with operations, reducing unnecessary pause and wait operations.

Inventive Principle:
Principle #23Feedback

3Productivity

If memory allocation is dynamically managed based on available cell counts, then memory utilization efficiency is improved, but access time increases due to dynamic checking

Engineering Contradiction:
Improvememory utilization efficiencyVSAvoidaccess time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by pre-establishing the shared memory structure and allocating cells before processes need to access them. The synchronization mechanisms pre-check and signal the availability status of memory cells, allowing processes to proceed with data transfer operations without dynamic checking delays during critical access phases, thus improving access time while maintaining efficient memory utilization.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12423032B2Systems and methods for implementing and using a cross-process queue within a single computer
Publication Date: 2025.09.23 SAS INSTITUTE INC
  • US12423032B2 patent drawing
  • US12423032B2 patent drawing
  • US12423032B2 patent drawing

AI summary

A system, method, and computer-program product includes implementing a cross-process queue within a single computer that is configured to transfer a data block between an operating system process executing a write operation and an operating system process executing a read operation, initializing in-memory cell indices within the cross-process queue that include a write operation index tracking index values of one or more cells within the cross-process queue that are available to write and a read operation index tracking index values of one or more cells within the cross-process queue that are available to read, and implementing a cell synchronization data structure tracking states of a plurality of cells of the index of cells of the cross-process queue.