Cross-Shaped DRAM Capacitor Layout for Higher Capacitance Density
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Solution Overview
Problem
Conventional DRAM capacitors have low capacitance density due to circular capacitor holes and traditional honeycomb close packing, leading to poor capacitor properties and larger device sizes.
Innovation Solution
A method for forming a capacitor with cross-shaped electrode layers arranged in a square close-packed manner, increasing capacitance density by using a semiconductor structure with a substrate, stacked layers, and etching through holes to create a cross-shaped electrode structure within the capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional circular capacitor holes with honeycomb close packing are used, then the manufacturing process is simple, but the capacitance density is low
Solution Approach 1:
The capacitor hole is segmented into multiple regions by dividing the circular hole into four quadrants, with electrode layers selectively formed in different regions. This segmentation allows increased electrode surface area within the same footprint, thereby improving capacitance density without significantly complicating the overall structure.
Solution Approach 2:
The invention transitions from a two-dimensional circular capacitor hole view to a three-dimensional stacked structure with multiple electrode layers at different heights (first electrode layer, second electrode layer, third electrode layer). This dimensional change enables increased capacitance by utilizing vertical stacking while maintaining the compact circular footprint.
2Area of moving object
If capacitor size is reduced to shrink DRAM device size, then device integration increases, but capacitance density decreases
Solution Approach 1:
Multiple electrode layers are nested within each other vertically, with the first electrode layer at a lower level, the second electrode layer at an intermediate level, and the third electrode layer at a higher level. This nesting arrangement allows the capacitor to maintain a small footprint area while achieving high capacitance through the stacked configuration.
Solution Approach 2:
The capacitor design moves from horizontal expansion to vertical stacking, utilizing the third dimension (height) to increase capacitance. By forming electrode layers at different vertical levels within the same planar footprint, the invention achieves high capacitance in a compact area suitable for scaled-down DRAM devices.
3Quantity of substance
If traditional honeycomb close packing is used, then layout is simple, but capacitor utilization is poor
Solution Approach 1:
The capacitor structure is segmented into multiple functional regions with different electrode layers positioned in specific quadrants. The first electrode layer occupies certain regions, the second electrode layer occupies other regions, and the third electrode layer occupies remaining regions. This segmentation improves capacitor utilization by ensuring that each region contributes effectively to the overall capacitance.
Solution Approach 2:
The layout transitions from a single-plane configuration to a multi-level stacked arrangement. By distributing electrode layers across different vertical levels and positioning them in different quadrants of the circular footprint, the invention maximizes the utilization of available space while maintaining a relatively simple circular layout pattern.
Data Source
AI summary
A method for forming a capacitor, the capacitor and a semiconductor device are provided. The method includes: providing a semiconductor structure including a substrate, a stacked-layer structure, a protective layer, a first mask layer, and a photolithography layer which is provided with a plurality of cross-shaped patterns arranged in a square close-packed manner; patterning the first mask layer based on the photolithography layer; forming a plurality of through holes penetrating through the protective layer and the stacked-layer structure based on the patterned first mask layer by etching, in which in a direction perpendicular to a surface of the substrate, a projection of each through hole is cross-shaped, and the plurality of through holes are arranged in the square close-packed manner; and forming a first electrode layer, a dielectric layer and a second electrode layer covering an inner wall of each through hole to form the capacitor.