Cross-Slot Transport Block Mapping With Multi-Slot Interleaving
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Solution Overview
Problem
Existing wireless communication systems face challenges in efficiently mapping transport blocks across slots allocated for uplink transmission in a physical shared channel, particularly in 5G networks, due to variations in resource allocation and slot configurations.
Innovation Solution
A transport block processing chain is introduced, incorporating a code block determination circuit and a rate matching circuit, along with an interleaver, to determine code block sizes and rate match bits across multiple slots, ensuring efficient mapping and interleaving across slot boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transport blocks are mapped across multiple slots with varying resource allocations, then resource utilization efficiency is improved, but the complexity of mapping and interleaving operations increases
Solution Approach 1:
The transport block is divided into multiple code blocks that can be independently mapped to different slots. Each code block is processed separately through rate matching and interleaving operations, allowing parallel processing and reducing overall complexity while enabling flexible cross-slot mapping for improved resource utilization.
Solution Approach 2:
The patent introduces a new dimension of operation by performing interleaving across slot boundaries rather than within single slots. The interleaver operates on a multi-slot basis, shuffling code block bits across different time resources, which enables more flexible resource allocation and improves utilization efficiency without significantly increasing processing complexity.
2Reliability
If code blocks are interleaved across slot boundaries, then data transmission robustness is improved, but the processing time and operational complexity increase
Solution Approach 1:
Code blocks are segmented and prepared for cross-slot interleaving in advance, before actual transmission. The rate matching and initial interleaving operations are performed on each code block separately, allowing the system to prepare data structures ahead of time and reduce real-time processing delays while maintaining robustness through distributed mapping across multiple slots.
Data Source
AI summary
A system and a method are disclosed relating to a transport block processing chain for a transmitter. A code block determination circuit may be configured to determine a size of a code block that maps across multiple slots of a wireless physical shared channel according to a Transport Block over Multiple Slots (TBoMS) configuration, and a rate matching circuit may be configured to rate match bits of the code block to a number of bits available in a transport block that spans the predetermined number of slots of the wireless physical shared channel. Additionally, an interleaver may be configured to interleave a continuous output of the rate matching circuit on a slot basis so that a code block that crosses a slot boundary between a first slot and a second slot is interleaved within the first slot and the second slot.