Cross-Stacked 3D Memory Chips to Limit Warpage

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Solution Overview

Problem

There is a need for semiconductor devices that enhance integration density and reliability, particularly in data storage systems, where existing technologies have limitations in increasing storage capacity and maintaining structural integrity.

Innovation Solution

The semiconductor device comprises a first memory chip structure with gate lines extending in a first horizontal direction and a second memory chip structure with gate lines extending in a perpendicular second horizontal direction, allowing for increased gate count and reduced deformation, thereby improving integration density and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are arranged three-dimensionally to increase storage capacity, then data storage capacity is improved, but device complexity increases

Engineering Contradiction:

Improvedata storage capacityVSAvoiddevice complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements three-dimensional memory cell arrangement by stacking multiple memory chip structures vertically. Each memory chip structure contains gate lines extending in horizontal directions with vertical memory structures penetrating through them, creating a 3D configuration that increases storage capacity while managing complexity through modular stacking

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory device is divided into multiple discrete memory chip structures stacked vertically, with each chip containing segmented gate lines and vertical memory structures. This segmentation allows independent fabrication and assembly of each layer, reducing overall device complexity while achieving high storage capacity

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If multiple memory chip structures are vertically stacked to improve integration density, then integration density is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveintegration densityVSAvoidmanufacturing precision

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The memory device is divided into multiple discrete memory chip structures that can be fabricated separately and then stacked vertically. Each chip structure is a self-contained unit with gate lines and vertical memory structures, allowing independent manufacturing and quality control, thereby reducing the precision requirements for the entire device

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple memory chip structures are nested vertically one on top of another, with each chip containing smaller-scale gate lines and vertical memory structures. This nested configuration achieves high integration density by充分利用 vertical space while maintaining manageable manufacturing precision for each individual chip layer

Inventive Principle:

Principle #7Nested doll (Nesting)

3Quantity of substance

If gate lines are stacked in vertical direction extending in horizontal directions to increase gate count, then integration density is improved, but structural deformation such as warpage increases

Engineering Contradiction:

Improvegate countVSAvoidstructural deformation

Core Design Contradiction:

Quantity of substanceVSStability of the object's composition

Solution Approach 1:

Gate lines in different memory chip structures extend in different horizontal directions (first horizontal direction for first memory chip, second horizontal direction perpendicular to first for second memory chip). This asymmetric arrangement distributes stress unevenly across the structure, reducing overall warpage while maintaining high gate count through vertical stacking

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS12166000B2Semiconductor device including a lower chip including a peripheral circuit and first and second memory chips vertically stacked thereon and data storage system including the same

Publication Date: 2024.12.10 SAMSUNG ELECTRONICS CO LTD

AI summary

The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.