Cross-Subframe Block Coding for High-Speed Error Correction
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Solution Overview
Problem
Existing error correcting methods using concatenated codes in high-speed digital transmission systems face challenges in maintaining high error correcting ability and minimizing circuit scale, as they often require separate circuits for inner and outer codes, leading to inefficient error correction and increased power consumption.
Innovation Solution
The proposed method involves generating and adding redundant data block code words across sub-frames, using a single interleaver and decoder to align and correct errors in both inner and outer code streams, ensuring every data bit is part of two error correcting code word streams, thereby enhancing error correction capability and reducing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If concatenated codes with separate inner and outer code circuits are used, then error correction is performed for both inner and outer codes, but the circuit scale increases and device complexity increases
Solution Approach 1:
The patent merges the separate inner code and outer code circuits into a unified error correction circuit. The same circuit performs both inner code correction (using syndrome calculation and lookup tables) and outer code correction (using iterative decoding), eliminating the need for duplicate circuitry and reducing overall device complexity while maintaining dual-code error correction capability
Solution Approach 2:
The error correction circuit is designed with multi-functionality to handle both inner code and outer code correction tasks. The circuit can switch between different correction modes (inner code syndrome-based correction and outer code iterative correction) and can process different code types (BCH, Reed-Solomon, LDPC) using the same hardware resources, thereby reducing circuit scale
2Reliability
If concatenated codes with separate inner and outer code circuits are used, then comprehensive error correction is achieved, but power consumption increases
Solution Approach 1:
By merging the inner and outer code correction functions into a single circuit, the patent eliminates redundant power consumption from duplicate circuit operations. The unified circuit shares computational resources, memory structures, and control logic, thereby reducing overall power consumption while maintaining comprehensive error correction capability
Solution Approach 2:
The patent implements a repeated decoding mechanism where the error correction circuit can discard incorrect correction attempts and recover by trying alternative decoding paths. The circuit uses iterative outer code correction with feedback, allowing it to recover from initial decoding failures without requiring separate dedicated circuits for each correction attempt, thus optimizing power usage
3Device complexity
If redundant data of inner code is not included in outer code, then inner code correction is simplified, but error correction ability decreases
Solution Approach 1:
The patent implements feedback mechanisms where the error correction circuit uses syndrome information from inner code correction and feeds it into the outer code correction process. The iterative decoding process continuously refines the correction by feeding back partial correction results and adjusting the decoding strategy, thereby achieving high error correction ability without requiring complex redundant data structures
Solution Approach 2:
The patent transitions from a simple hierarchical code structure to a more sophisticated multi-dimensional correction approach. The error correction circuit operates in multiple dimensions: inner code syndrome dimension, outer code iterative dimension, and cross-code feedback dimension. This dimensional expansion allows the system to achieve superior error correction without increasing the complexity of the underlying coding structure
Data Source
AI summary
An error correcting method for correcting an error of digital data is provided. The method includes a plurality of sub-frames including a plurality of block code words, including: extracting and aligning a block code word, which is included in a past sub-frame; and generating a redundant data block code word by use of a block code word, which is included in a latest sub-frame, and the aligned block code word, and adding the redundant data block code word to the latest sub-frame, wherein the redundant data block code word is used for generating a redundant data block code word, which is added to a next sub-frame.