Modified Cross-Sum Logic Circuit for Scalable Mersenne Division
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Solution Overview
Problem
Existing digital circuits for performing divisions by Mersenne numbers are complex and not scalable, and integer division methods involve significant calculating effort with potential rounding issues.
Innovation Solution
A logic circuit that calculates a quotient based on a modified cross-sum of a bit-wise inverted input word, using a chain of M-bit adders with specific connections and inputs, allowing for scalable and efficient division operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a divider circuit is designed to perform division by a Mersenne number, then the division operation can be achieved, but the circuit becomes complex and not scalable to different number of digits
Solution Approach 1:
The division operation is segmented into N independent M-bit adders, each handling one digit of the dividend. This segmentation allows the circuit to process different numbers of digits by simply adjusting N, making the circuit scalable without increasing complexity proportionally to the number of digits.
Solution Approach 2:
Each M-bit adder is designed to perform multiple functions: it processes one digit of the dividend, handles carry propagation to the next digit, and contributes to the final quotient calculation. This universal design allows the same circuit structure to be reused for different digit lengths, enhancing scalability.
2Productivity
If long division algorithms are used for integer division, then the division can be performed, but the calculating effort is considerable
Solution Approach 1:
The patent replaces the mechanical long division process with a parallel adder-based system. Instead of sequential subtraction and shift operations, the circuit uses simultaneous addition operations across multiple adders, dramatically reducing the calculating effort and time required for division.
Solution Approach 2:
The circuit performs preliminary bit-wise inversion of the dividend to create the input word CP, which is then processed by the adder chain. This preliminary transformation simplifies the subsequent addition operations and enables the circuit to compute the quotient more efficiently without requiring iterative long division steps.
3Productivity
If multiplication by a precalculated fix-point constant is used for division, then the calculating effort is reduced, but rounding issues may occur
Solution Approach 1:
Instead of using approximate fix-point multiplication, the patent creates an exact copy of the dividend digits through the adder chain, where each adder processes one digit and propagates carries exactly. This copying mechanism preserves precision without rounding errors while maintaining low calculating effort.
Data Source
AI summary
A logic circuit configured to calculate a quotient Q based on a modified cross-sum of an input word CP, a digital circuit having a first input for the input word CP that is a bit-wise inverted value of a number N of M-bit digits having a radix 2M from a least significant digit to a most significant digit, the circuit configured to calculate a quotient Q, M and N being positive integer numbers larger than one, wherein the digital circuit has a second input RIN that is configured to be set to zero, or to receive a remainder value from another logic circuit, and wherein the digital circuit provides for an output word Q having N digits, each digit of radix 2M, the output word Q being a raw quotient of the bit-wise inverted value of the input word CP.