Cross-threaded Memory System for Parallel Graphics Processing
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Solution Overview
Problem
Modern gaming systems face challenges in increasing memory bandwidth due to physical limits on pin count and signaling rate, leading to performance penalties when multiple graphics controllers contend for shared data structures in graphics pipelines.
Innovation Solution
A cross-threaded memory system is implemented, where multiple memory access requestors can concurrently access shared memory devices through buffer ICs and memory devices, using a round-robin memory access scheme to enable parallel processing without idle periods, by switching between memory devices and controllers via a channel select signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If additional graphics controllers are added to increase parallel processing, then processing capacity is improved, but performance penalty occurs due to contention for shared data structures
Solution Approach 1:
The shared memory is segmented into multiple separate memory banks, allowing different graphics controllers to access different banks simultaneously. This eliminates contention for shared data structures by providing dedicated memory resources to each controller, thus maintaining parallel processing capacity without performance penalties.
Solution Approach 2:
A memory management intermediary is introduced that arbitrates and manages access between multiple graphics controllers and the memory banks. This intermediary coordinates access patterns to ensure that controllers can operate in parallel while maintaining data consistency, reducing waiting time through intelligent scheduling.
2Productivity
If pin count or signaling rate is increased to improve memory bandwidth, then memory bandwidth is improved, but physical limits are approached making further increases difficult
Solution Approach 1:
The memory system is segmented into multiple independent memory banks, each accessible through separate pathways. This segmentation allows the total memory bandwidth to be distributed across multiple channels, achieving high aggregate bandwidth without requiring excessive pins or signaling rate on any single channel.
Solution Approach 2:
Instead of increasing bandwidth in a single dimension (higher pin count or signaling rate), the system transitions to a multi-dimensional approach by adding multiple memory banks and access pathways. This dimensional expansion allows bandwidth scaling without proportionally increasing pin count or signaling complexity.
Data Source
AI summary
A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.