Cross-Tier Word Line Layout to Reduce Memory Coupling
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Solution Overview
Problem
As semiconductor memory devices shrink in size, the reduced pitch between memory cells leads to increased coupling effects between word lines, resulting in reduced word line speed and integrated circuit performance.
Innovation Solution
The memory device incorporates a memory cell array with word lines on odd-numbered tiers oriented differently from those on even-numbered tiers, reducing cell-to-cell spacing and minimizing the coupling effect between stacked tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the pitch between memory cells is reduced to shrink device size, then the device size is minimized, but the coupling effect between word lines increases
Solution Approach 1:
The patent applies asymmetry by orienting word lines on odd-numbered tiers in a first direction and word lines on even-numbered tiers in a second direction that is angularly offset from the first direction. This asymmetric angular offset between stacked tiers breaks the symmetry of direct alignment, thereby reducing the coupling effect between adjacent word lines while maintaining minimal device size.
Solution Approach 2:
The patent introduces a new dimensional parameter by varying the angular orientation of word lines across different tiers. Instead of maintaining parallel alignment in the same plane, the word lines are rotated at different angles in the vertical stacking dimension, effectively using angular orientation as an additional degree of freedom to reduce coupling while preserving compact footprint.
2Quantity of substance
If the spacing between word lines is reduced to increase density, then the integration density is improved, but the word line speed decreases
Solution Approach 1:
The asymmetric angular offset between word lines on adjacent tiers reduces parasitic coupling capacitance between closely spaced word lines. This allows the patent to maintain reduced word line spacing for high integration density while mitigating the speed degradation that would normally result from increased coupling effects.
3Ease of manufacture
If word lines on adjacent tiers are aligned parallel to each other, then the manufacturing process is simplified, but the coupling effect between tiers increases
Solution Approach 1:
The patent deliberately introduces asymmetric angular offset between word lines on adjacent tiers, deviating from the simpler parallel alignment approach. While this increases manufacturing complexity slightly, it effectively reduces the coupling effect between tiers, demonstrating that the asymmetric configuration successfully resolves the contradiction between ease of manufacture and coupling reduction.
Data Source
AI summary
A memory device includes a memory cell array. The memory cell array includes first-tier word lines extending in a first direction, second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction, and bit lines extending in a third direction angularly offset from the first and second directions. The bit lines are arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.