Cross Trace Circuit for Multi-Processor Debug Bandwidth
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Solution Overview
Problem
Current multi-processing systems face challenges in efficiently capturing and combining trace data from multiple processors due to high bandwidth requirements and the impracticality of serial output, which overwhelms existing systems, and existing solutions fail to effectively address the need for debugging in multi-processing environments.
Innovation Solution
The implementation of an electronic circuit with cross trace circuits and state machines that detect specific processing operations across multiple processors, allowing for the efficient capture and export of trace data by coupling trace buffers to a common output, and utilizing a trace combiner circuit to reduce bandwidth requirements and enhance debug capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trace data from multiple processors is captured and combined using independent free-running trace streams, then complete processing activity is recorded, but bandwidth requirements become overwhelmingly high and impractical for current systems
Solution Approach 1:
The patent applies preliminary action by implementing triggering circuits that pre-detect specified processing operations before they complete. When a trigger condition is met (such as a specific instruction execution or processor event), the system prepares to capture trace data only for relevant processors and time periods, preventing the need to continuously capture and store all processor activity. This reduces the total volume of trace data that must be handled while ensuring complete capture of debug-relevant information.
2Loss of information
If serial output is used to export trace data from high-speed processors, then data can be transmitted externally, but the clock rate required becomes impractically high (e.g., 19.2 GHz for a single processor)
Solution Approach 1:
The patent applies segmentation by dividing the trace data export function across multiple parallel output channels rather than using a single high-speed serial port. Each processor or processor group has its own dedicated trace output path with manageable clock rates. The trace combiner circuit then merges these segmented streams, allowing external systems to reconstruct complete trace information without requiring any single serial interface to operate at impractically high speeds.
Solution Approach 2:
The patent implements merging by combining trace streams from multiple processors into a single coordinated output using a trace combiner circuit. This combiner synchronizes and merges the segmented trace data streams, allowing the system to export complete multi-processor trace information through multiple parallel channels at moderate speeds, rather than requiring one extremely high-speed serial interface.
3Quantity of substance
If on-chip compression is used to reduce trace bandwidth by a factor of 10, then bandwidth requirements decrease to 240 MB/sec, but compression complexity and processing overhead increase
Solution Approach 1:
The patent applies taking out by extracting only the essential debug information from processor activity rather than compressing all trace data. The triggering circuits identify and extract only those processing operations that meet specified debug criteria, eliminating the need for compression of irrelevant data. This extraction approach reduces bandwidth requirements without requiring complex compression algorithms or circuits.
4Measurement precision
If cross-triggering is implemented to detect sequences across multiple processors, then debug information quality improves, but the complexity of trigger coordination and state management increases
Solution Approach 1:
The patent introduces an intermediary trace combiner circuit that mediates between multiple processor triggering circuits and the external debug system. This combiner receives trigger signals from various processors, coordinates their state machine operations, and manages the merging of trace streams. By centralizing coordination functions in this intermediary component, the system achieves precise cross-processor debugging capability without distributing complex coordination logic across all processors.
Data Source
AI summary
An electronic circuit includes a first processor (100) operable to perform processing operations, a first trace buffer (230) coupled to the first processor (100), a first triggering circuit (210) coupled to the first processor (100), the first triggering circuit (210) operable to detect a specified sequence of particular processing operations in the first processor (100); a second processor (101), a second trace buffer (231) coupled to the second processor (101), a second triggering circuit (211) coupled to the second processor (101), the second triggering circuit (211) operable to detect at least one other processing operation in the second processor (101); and a cross trace circuit (330) having a trace output and having inputs coupled to the first triggering circuit (210) and to the second triggering circuit (211), the cross trace circuit (330) configurably operable to respond to a sequence including both a detection of the sequence of particular processing operations of the first processor (100) by the first triggering circuit (210) and a detection of the at least one other processing operation of the second processor (101) by the second triggering circuit (211), to couple at least one of the first trace buffer (230) and the second trace buffer (231) to the trace output. Various circuits, devices, telecommunications products, wireless handsets, systems and processes of operation and manufacture are disclosed.