Register Transfer Execution Circuit for Cross-Type Fusion

Solution Overview

Problem

Modern processors face inefficiencies in executing instructions that involve data transfer between different types of execution circuits, such as integer and floating-point circuits, due to the need for 'dummy load operations' that increase latency and resource consumption.

Innovation Solution

Implement parallel execution paths in the load/store circuit, including a memory execution circuit and a register transfer execution circuit, to execute instructions specifying data transfer between different types of execution circuits and an operation to be performed on the data, using a replicated version of execution logic in the register transfer execution circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If separate execution units are used for integer and floating-point instructions, then instruction execution can be specialized and optimized, but data transfer between different execution unit types requires dummy load operations that increase latency and resource consumption

Engineering Contradiction:

Improveinstruction execution efficiencyVSAvoidexecution latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent merges the data transfer operation and the subsequent execution operation into a single fused instruction operation. When the processor detects that a load/store operation is followed by an execution operation on the same data, it combines these two separate operations into one fused operation that can be executed without intermediate dummy load operations, thereby reducing latency and improving execution efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The processor performs preliminary detection of instruction sequences that qualify for fusion before execution. By identifying candidate fused operations in advance and preparing them for fusion, the system can eliminate the need for dummy load operations that would otherwise be required, thus reducing execution latency while maintaining the benefits of specialized execution units.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If separate execution units are used for integer and floating-point instructions, then each unit can be optimized for its specific task, but the need for dummy load operations increases resource consumption

Engineering Contradiction:

Improveexecution accuracyVSAvoidresource consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent merges the data transfer operation and the subsequent execution operation into a single fused instruction operation. When the processor detects that a load/store operation is followed by an execution operation on the same data, it combines these two separate operations into one fused operation that can be executed without intermediate dummy load operations, thereby reducing latency and improving execution efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent eliminates unnecessary dummy load operations that consume resources without performing useful work. By discarding these redundant operations through fusion, the system recovers resources that would otherwise be wasted, reducing overall energy consumption while maintaining execution accuracy through the preserved specialized execution units.

Inventive Principle:

Principle #34Discarding and recovering

3Adaptability or versatility

If dummy load operations are used for data transfer between execution units, then data can be moved between different execution unit types, but execution latency increases

Engineering Contradiction:

Improvedata transfer capabilityVSAvoidexecution throughput

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges the data transfer operation and the subsequent execution operation into a single fused instruction operation. When the processor detects that a load/store operation is followed by an execution operation on the same data, it combines these two separate operations into one fused operation that can be executed without intermediate dummy load operations, thereby reducing latency and improving execution efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent enables continuous useful action by eliminating idle dummy load operations between data transfer and execution. Through fusion, the system ensures that data transfer and execution operations are seamlessly connected without interruption, maintaining continuous productive work flow and improving overall execution throughput while preserving the adaptability of data transfer between different execution unit types.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20250284496A1Operation Fusion for Instructions Bridging Execution Unit Types

Publication Date: 2025.09.11 APPLE INC

AI summary

Techniques are disclosed that relate to fusing operations for execution of certain instructions. A processor may include a first execution circuit, of a first type, coupled to a first register file, a second execution circuit, of a second type, coupled to a second register file and a load/store circuit coupled to the first and second register files. The load/store circuit includes an issue port configured to receive an instruction operation for execution, a memory execution circuit configured to execute memory access operations, and a register transfer execution circuit. The register transfer execution circuit is configured to execute instruction operations specifying data transfer from the first register file to the second register file and an operation to be performed using the data, and the load/store circuit is configured to direct a given instruction operation from the issue port to one of the memory execution circuit or the register transfer execution circuit.