Cross-Validating Subsystem Memory Regions for Security

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Solution Overview

Problem

Conventional computer security methods fail to detect and report security breaches effectively, allowing compromised systems to remain undetected and potentially spread attacks through networks, as they rely on single-point validation that can be compromised by malicious actors.

Innovation Solution

Implementing a cross-validation method using multiple subsystems, where each subsystem verifies the security of another without authority to make changes, requiring simultaneous compromise of both to bypass security checks, thereby preventing system startup and network connection in case of a breach.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single cryptographic hash validation is performed on non-volatile memory, then the validation process is simple and fast, but the security reliability is insufficient as a single point of compromise can breach the entire system

Engineering Contradiction:
Improvesecurity reliabilityVSAvoidvalidation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system divides the validation function into multiple independent subsystems (first subsystem and second subsystem), each performing validation on the other's data. This segmentation ensures that a single point of compromise cannot breach the entire system, as each subsystem can detect compromises in the other independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary validation mechanism where each subsystem acts as a validator for the other. The first subsystem validates data from the second subsystem and vice versa, creating a mutual verification system that enhances security without requiring a central authority.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If conventional single-subsystem validation is used, then the system operation is simple, but the system cannot detect or report security breaches effectively

Engineering Contradiction:
Improvebreach detection capabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system implements feedback mechanisms where each subsystem reports validation results to the other. When the first subsystem validates data from the second subsystem, it generates feedback about the security status, enabling the system to detect and report breaches effectively through this mutual feedback loop.

Inventive Principle:
Principle #23Feedback

3Object-affected harmful factors

If a compromised system continues to operate without detection, then system availability is maintained, but the attack can spread through the network

Engineering Contradiction:
Improveattack spread preventionVSAvoidsystem availability
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The system performs preliminary validation checks before allowing operations to proceed. By validating data integrity upfront through cross-subsystem verification, the system prevents compromised data from being processed or spread, thereby stopping attacks before they can propagate through the network.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS7594124B2Cross validation of data using multiple subsystems
Publication Date: 2009.09.22 INTEL CORP
  • US7594124B2 patent drawing
  • US7594124B2 patent drawing
  • US7594124B2 patent drawing

AI summary

A method and apparatus for cross validation of data using multiple subsystems are described. According to one embodiment of the invention, a computer comprises a first subsystem and a second subsystem; and a memory, the memory comprising a first memory region and a second memory region, the first memory region being associated with the first subsystem and a second memory region being associated with the second subsystem; upon start up of the computer, the first subsystem to validate the second memory region and the second subsystem to validate the first memory region.