Cross-Wafer RDL Layout for Higher I/O Density in Reconstructed Wafers
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in increasing I/O pad density due to smaller die sizes, leading to limitations in fan-in packages and solder ball density, and inefficiencies in packaging defective dies.
Innovation Solution
The formation of cross-wafer Redistribution Lines (RDLs) that connect package components directly in reconstructed wafers, bypassing the need for device dies and solder regions, allowing for longer tracing lengths and increased I/O pad density through wafer-level lithography and plating processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fan-in package is used with smaller die sizes, then throughput is improved and cost is reduced, but the number of I/O pads is limited due to pitch constraints and solder bridge risks
Solution Approach 1:
The patent transitions from two-dimensional pad layout on the die surface to three-dimensional redistribution layers (RDLs) stacked above and below the die. Multiple RDL layers allow I/O pads to be redistributed vertically, dramatically increasing the effective number of I/O connections without increasing the die footprint or pad pitch density.
Solution Approach 2:
The patent introduces redistribution layers (RDLs) as an intermediary structure between the die pads and the external package pins. These RDLs act as a mediator that redistributes the limited die pads to a larger number of package pins, enabling fan-out packaging that overcomes the direct one-to-one mapping limitation of fan-in packages.
2Quantity of substance
If I/O pad pitch is decreased to increase pad density, then number of I/O pads is increased, but solder bridges may occur
Solution Approach 1:
The patent moves the I/O pad redistribution function from the horizontal plane (die surface) to the vertical dimension (multiple RDL layers). This allows increased I/O capacity without decreasing the pitch between adjacent pads on the die surface, thereby maintaining reliable solder connections while achieving higher pad counts through vertical stacking of conductive layers.
3Quantity of substance
If fan-out package is used to increase I/O pad density, then number of I/O pads is increased, but packaging process becomes more complex and defective dies cannot be efficiently handled
Solution Approach 1:
The patent performs wafer-level testing and sorting before the packaging process, identifying and separating defective dies in advance. This preliminary action ensures that only known-good dies proceed through the complex fan-out packaging process with multiple RDL layers, improving efficiency and reducing waste while maintaining the capability for high I/O density.
4Reliability
If cross-wafer RDLs are formed to connect package components directly, then resistance is reduced and signal integrity is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent combines multiple packaging functions into a single integrated structure: the RDL layers simultaneously serve as interconnect pathways, signal transmission media, and mechanical support structures. By merging these functions into unified stacked layers rather than separate components, the patent achieves low resistance and high signal integrity while managing manufacturing complexity through integration rather than assembly of multiple discrete elements.
Data Source
AI summary
A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.