Non-Blocking Crossbar Buffer for Concurrent Packet Access

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Solution Overview

Problem

Existing configurable logic integrated circuits face inefficiencies in data transfer and processing, particularly in big-data and fast-data applications, due to blocking issues in data transfers through crossbar buffer circuits, leading to bandwidth constraints and data congestion.

Innovation Solution

Implementing a non-blocking crossbar buffer circuit that allows concurrent access to data packets by both processing and accelerator circuits without blocking, reducing the need to transfer entire packets and optimizing data movement through intelligent packet handling and control logic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional blocking data access is used in configurable logic integrated circuits, then data transfer simplicity is maintained, but data processing speed and system productivity deteriorate due to blocking issues

Engineering Contradiction:

Improvedata processing speedVSAvoidbuffer circuit complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The buffer circuit is segmented into multiple independently controllable buffer elements (first buffer element, second buffer element, etc.), each associated with specific input/output ports. This segmentation allows concurrent access to different data packets without blocking, as each buffer element can be independently controlled by control logic to grant or deny access based on arbitration decisions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The buffer circuit implements dynamic control through control logic that continuously arbitrates between processing circuit and accelerator circuit access requests. The control logic dynamically adjusts buffer element accessibility in real-time, switching between blocking and non-blocking states based on current system needs, thereby achieving high-speed concurrent access without permanent structural complexity.

Inventive Principle:

Principle #15Dynamics

2Productivity

If high bandwidth is provided for data transfer between processing and accelerator circuits, then data transfer capability is improved, but bandwidth requirements and system resource consumption increase

Engineering Contradiction:

Improvedata transfer capabilityVSAvoidbandwidth requirements

Core Design Contradiction:

ProductivityVSQuantity of substance

Solution Approach 1:

The buffer circuit serves as an intermediary data storage structure between the processing circuit and accelerator circuit. Instead of requiring high-bandwidth direct communication channels, the buffer circuit stores data packets and allows both circuits to access the buffer at lower bandwidth rates independently, eliminating the need for high-bandwidth direct transfer paths while maintaining high overall data transfer capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

Data packets are pre-loaded into the buffer circuit before being needed by either the processing circuit or accelerator circuit. This preliminary action allows both circuits to access data independently without requiring high-bandwidth real-time transfer, as the data is already positioned in the buffer ready for retrieval at lower bandwidth rates.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If entire data packets are transferred between circuits, then data integrity is maintained, but data movement volume and power consumption increase

Engineering Contradiction:

Improvedata integrityVSAvoidpower efficiency

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The control logic extracts only the necessary portions or specific data packets from the buffer circuit and transfers them selectively to the processing circuit or accelerator circuit. Instead of transferring entire data packets or all available data, the system extracts only what is currently needed, maintaining data integrity for stored packets while reducing the volume of data movement and associated power consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

4Adaptability or versatility

If shared buffer access is implemented between processing and accelerator circuits, then system flexibility is improved, but access control complexity increases

Engineering Contradiction:

Improvesystem flexibilityVSAvoidaccess control logic complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The buffer circuit is designed as a universal shared resource that can serve multiple functions and multiple circuits (both processing circuit and accelerator circuit). The control logic implements universal access control rules that apply regardless of which circuit requests access, simplifying the control architecture compared to having separate dedicated buffers. This multi-functionality approach achieves high system flexibility while managing access control complexity through standardized control logic.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12607977B2Shared non-blocking crossbar buffer circuits and methods

Publication Date: 2026.04.21 ALTERA CORP

AI summary

A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.