Crossbar DWA Circuit for Faster Dynamic Element Matching
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Solution Overview
Problem
High-speed data converters employing data weighted averaging (DWA) algorithms for first-order dynamic element matching face challenges such as cumbersome operation, high conversion time, inefficient circuit implementation, and increased complexity due to the need for decoder and adder logic, as well as multiple parallel paths for interleaving, which negatively impact throughput and performance.
Innovation Solution
A crossbar switch matrix controlled by a crossbar selection signal, combined with a data register and a control circuit that determines bit locations for logic transitions, enables efficient data weighted averaging by selectively mapping input to output bits, thereby achieving dynamic element matching without the need for complex decoder and adder logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DWA algorithm with decoder and adder logic is used, then dynamic element matching is achieved, but device complexity and conversion time increase
Solution Approach 1:
The patent extracts and removes the complex decoder and adder logic from the DWA algorithm implementation. Instead of using traditional computational units, the invention uses a simplified lookup table approach where pre-calculated DWA values are stored and directly selected based on input codes, eliminating the need for real-time decoding and addition operations.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and storing all possible DWA algorithm results in lookup tables before runtime. The tables contain pre-computed mapping relationships between input codes and corresponding output element selections, allowing the system to perform simple table lookups during operation rather than executing complex calculations in real-time.
2Reliability
If traditional DWA algorithm with multiple parallel paths is used, then dynamic element matching is achieved, but productivity and throughput decrease
Solution Approach 1:
The patent segments the DWA algorithm implementation into separate lookup tables for different bit positions (LSB, middle bits, MSB). Each table handles a specific segment of the conversion process, allowing parallel access and selection without requiring sequential processing through multiple parallel computational paths, thereby improving throughput.
3Reliability
If traditional DWA algorithm is used, then dynamic element matching is achieved, but conversion time increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing all possible DWA algorithm results in lookup tables before runtime. The tables contain pre-computed mapping relationships between input codes and corresponding output element selections, allowing the system to perform simple table lookups during operation rather than executing complex calculations in real-time.
Solution Approach 2:
The patent replaces the mechanical/computational system of decoder and adder logic with a memory-based lookup system. Instead of using computational units that perform sequential operations, the invention uses pre-stored tables that allow direct address and immediate retrieval of results, significantly reducing conversion time.
Data Source
AI summary
A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.