Crossbar Memory Circuit Defect Relief via Polarity Inversion
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Solution Overview
Problem
Variable resistance elements in crossbar switch type memory circuits and look-up table circuits often enter defect states such as open, short, or intermediate resistance states during programming, leading to malfunction and excessive standby current due to insufficient resistance values, making it difficult to maintain circuit functionality.
Innovation Solution
A crossbar switch type memory circuit design that includes power supply-side and ground-side transistors with polarity control lines, along with a logic inversion circuit, to manage the resistance states of variable resistance elements, ensuring normal operation even when defects occur by inverting the polarity signal and reprogramming when read and write data do not match.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If variable resistance elements are used in crossbar switch type memory circuits, then integration degree and area efficiency are improved, but reliability deteriorates due to defect states such as open, short, and intermediate resistance states
Solution Approach 1:
The memory circuit is divided into multiple blocks, each containing variable resistance elements with defect relief circuits. This segmentation allows defective elements to be isolated and compensated within individual blocks without affecting the entire circuit, thereby maintaining reliability while preserving area efficiency.
Solution Approach 2:
Defect relief circuits are pre-configured in each memory block to compensate for potential defects in variable resistance elements. These circuits include transistors and wiring arranged to automatically mitigate the effects of open, short, or intermediate resistance states before they can cause circuit malfunction, thus ensuring reliability while maintaining the compact crossbar switch structure.
2Reliability
If variable resistance elements are programmed to achieve desired resistance states, then memory functionality is improved, but harmful factors increase due to excessive standby current from intermediate resistance states
Solution Approach 1:
The defect relief circuits convert the harmful effect of intermediate resistance states (excessive standby current) into a manageable condition by detecting the defective state and automatically switching alternative conduction paths. This transforms the harmful current leakage into a controlled signal that triggers compensation, thereby eliminating the harmful effect while maintaining memory functionality.
Solution Approach 2:
Transistors in the defect relief circuits act as intermediaries between the variable resistance elements and the power supply. When intermediate resistance states cause excessive current, these intermediary transistors switch to block or redirect the current flow, preventing the harmful effect from reaching the power supply while preserving the memory element's data storage function.
3Device complexity
If conventional crossbar switch configuration is used, then device complexity is reduced, but reliability deteriorates when variable resistance elements enter defect states
Solution Approach 1:
The defect relief functionality is merged with the existing crossbar switch memory blocks by integrating additional transistors and wiring within the same block structure. This merging approach adds defect compensation capability without requiring separate dedicated circuits, thus limiting the increase in device complexity while significantly improving reliability under defect conditions.
Solution Approach 2:
The defect relief circuits are designed with universal applicability across all memory blocks, using the same transistor configurations and wiring patterns in each block. This universal design allows the circuit to handle multiple types of defects (open, short, intermediate resistance states) with a single standardized solution, minimizing the increase in overall device complexity while providing comprehensive reliability improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for normal operation of the crossbar switch type memory circuit even when variable resistance elements are in defect states, improving reliability by detecting and mitigating defects through data inversion and reprogramming, thus preventing malfunctions and excessive current flow.
Implementation Method 1
a variable resistance element using the movement of metal ions and electrochemical reactions with the use of a solid (ion conductor) in which ions can freely move by application of an electric field
Implementation Method 2
The variable resistance element is composed of an ion conduction layer, and a first electrode and a second electrode arranged with the ion conduction layer sandwiched therebetween. In this case, metal ions are supplied from the first electrode to the ion conduction layer
Data Source
AI summary
In order to provide a crossbar switch type memory circuit designed to be usable in normal circumstances even when a resistance change element is in an adverse state, the present invention is provided with: a first unit including a first column wiring to which one end of a first resistance change element is connected, a first power supply-side transistor for controlling the connection of the first column wiring and a power supply node, a first ground-side transistor, of a reverse operation type to the first power supply-side transistor, for controlling the connection of the first column wiring and a ground node, and a first polarity control line for causing the first power supply-side transistor or the first ground-side transistor to turn on and the other to turn off by a polar signal from a polar signal terminal, the first polarity control line being connected to the control terminals of the first power supply-side transistor and first ground-side transistor; a second unit including a second column wiring to which one end of a second resistance change element is connected, a second power supply-side transistor, of the same operation type as the first power supply-side transistor, for controlling the connection of the second column wiring and the power supply node, a second ground-side transistor, of a reverse operation type to the second power supply-side transistor, for controlling the connection of the second column wiring and the ground node, a logic inversion circuit for inverting the polarity of the polar signal from the polar signal terminal and outputting the polarity-inverted signal, and a second polarity control line for causing the second power supply-side transistor or the second ground-side transistor to turn on and the other to turn off by a polar signal from the logic inversion circuit, the second polarity control line being connected to the control terminals of the second power supply-side transistor and second ground-side transistor; and n row wirings (n: positive integer) to which the other ends of the first and second resistance change elements are connected.