Scalable Crossbar Memory Architecture Using Variable Packet Segmentation
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Solution Overview
Problem
Current memory architectures in crossbar switches are not scalable as the number of ports increases, leading to bandwidth challenges and inefficiencies in handling packets of varying lengths, particularly due to head-of-line blocking and the need for high-bandwidth shared memory.
Innovation Solution
The implementation of input buffers with a fixed number of banks defined by a preselected buffer size ratio to the smallest packet size, allowing for storage and transfer of packet subsegments across a shared memory, enabling efficient handling of packets of variable lengths by synchronizing and aligning data across input and output buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If output queuing is used to overcome head-of-line blocking, then packet loss is prevented, but the number of memory instances grows at least as fast as n2, making the system non-scalable
Solution Approach 1:
The patent segments packets into fixed-size cells (e.g., 64-byte cells) that can be independently processed and stored. Instead of queuing entire variable-length packets, the system divides packets into uniform cells that fit into fixed-size memory locations, enabling scalable memory architecture where memory requirements grow linearly rather than quadratically with the number of ports.
Solution Approach 2:
The patent changes the fundamental parameter from variable-length packets to fixed-length cells. By standardizing the data unit size to match memory word size (e.g., 64 bytes), the system transforms the memory access pattern from variable to fixed, enabling efficient use of shared memory and reducing the total memory capacity needed while preventing packet loss through proper cell-level buffering and reassembly.
2Productivity
If shared memory bandwidth is increased to support high port counts, then aggregate throughput is improved, but bandwidth requirements become prohibitively high and difficult to implement
Solution Approach 1:
By segmenting packets into fixed-size cells, the patent enables parallel processing of multiple cells simultaneously. The shared memory can service multiple cell requests in parallel at lower individual bandwidth rates, achieving high aggregate throughput without requiring prohibitively high peak bandwidth. The fixed cell size allows for efficient memory banking and parallel access patterns.
Solution Approach 2:
The patent implements periodic cell transmission where cells are transferred in synchronized time slots between input buffers, shared memory, and output buffers. This periodic action allows the memory system to operate at manageable bandwidth rates while achieving high aggregate throughput through continuous periodic transfers rather than bursty high-bandwidth requirements.
3Device complexity
If fixed buffer sizes are used to simplify memory architecture, then device complexity is reduced, but efficiency in handling variable packet sizes deteriorates
Solution Approach 1:
The patent resolves this contradiction by segmenting variable-length packets into fixed-size cells. The fixed cell size matches the fixed buffer size, eliminating the mismatch problem. Multiple cells from the same packet are distributed across multiple fixed-size buffer locations, and the original packet is reassembled at the output by collecting cells in sequence. This maintains both architectural simplicity and handling efficiency.
Solution Approach 2:
The patent introduces fixed-size cells as an intermediary between variable-length packets and fixed-size buffers. Cells serve as the common data unit that bridges the gap between variable packet sizes and fixed buffer structures, enabling efficient storage, retrieval, and reassembly without sacrificing either simplicity or efficiency.
Data Source
AI summary
Packets or cells of variable lengths arriving at a multitude of input ports of a crossbar switch are stored in the input buffers associated with the input ports. Each input buffer includes a number of banks defined by a ratio of a preselected size to the smallest packet size. Each bank is configured to store a packet having the smallest size. The packets so stored in the buffers are subsequently transferred and stored in a memory shared by all the input and output buffers. The packets are stored along the depth of the shared memory, therefore, during each packet transmission period, a portion of each one of the packets is transferred and stored in the same addressable storage location of the share memory. Each portion includes one or more bits carried by the packet.