Crossbar Memory Encoding to Reduce Voltage Drops
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Solution Overview
Problem
Crossbar memory arrays face inefficiencies due to sneak or leakage current, which increases energy consumption and reduces switching speed by causing voltage drops across half-selected cells, particularly affecting cells farther from the voltage source.
Innovation Solution
The proposed method involves encoding data to minimize voltage drops by mapping more low resistance states closer to the voltage source within the crossbar memory array, using a word pattern arrangement that flips the bit pattern to reduce sneak or leakage current, and storing an additional bit to indicate the arrangement for decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data is mapped to cells in a crossbar memory array without considering position, then the memory array can be accessed, but voltage drops due to sneak or leakage current increase energy consumption and reduce switching speed
Solution Approach 1:
The patent applies local quality by differentiating the treatment of bit patterns based on their position within the memory array. Specifically, it identifies whether low resistance states are concentrated in the first half or second half of the bit pattern and applies different encoding strategies accordingly. This localized approach optimizes each region's contribution to overall energy consumption and switching speed
Solution Approach 2:
The patent employs inversion by flipping the bit pattern when low resistance states are detected in the second half of the sequence. This reversal strategy repositions problematic low resistance states to more favorable locations, thereby reducing sneak current paths and minimizing voltage drops that would otherwise increase energy consumption and degrade switching speed
2Quantity of substance
If crossbar memory array size is increased, then more data can be stored, but cumulative current draw and parasitic losses increase
Solution Approach 1:
The patent changes the encoding parameters of data stored in the crossbar memory array by flipping bit patterns based on the distribution of low resistance states. This parameter transformation reduces the cumulative current draw across the array, enabling larger memory capacities to be implemented without proportionally increasing parasitic losses and energy consumption
3Area of stationary object
If cells farther from the voltage source are used, then more cells can be addressed in the array, but voltage drops reduce switching performance
Solution Approach 1:
The patent performs preliminary action by analyzing the bit pattern before writing data to the memory array. It detects the distribution of low resistance states and determines whether flipping is necessary to optimize performance. This pre-processing step ensures that data is encoded in a way that minimizes voltage drops before the actual memory operation, thereby maintaining switching speed across the entire array area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances switching speed, reduces power consumption, and improves memory performance by minimizing cumulative current draw and parasitic losses, allowing for larger crossbar memory array sizes with increased accuracy.
Implementation Method 1
The memory elements may be programmed to a low resistance state or a high resistance state, according to a respective bit value of the encoded bits
Data Source
AI summary
In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.