Crossbar In-Memory Computing with Split MSB/LSB Noise Reduction
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Solution Overview
Problem
Analog in-memory computing (AIMC) for deep neural networks (DNNs) suffers from a lower signal-to-noise ratio (SNR) due to process, voltage, and temperature (PVT) variations, which affects the accuracy and performance of subsequent DNN operations.
Innovation Solution
Implementing a mixed analog/digital in-memory computing system with noise reduction techniques, including a cross-bar array of analog cells, where digital multipliers are split into most significant (MS) and least significant (LS) portions, and using input and output peripheral circuits to preprocess and combine partial sums to form a resulting value with reduced noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If analog in-memory computing is used for DNN acceleration, then computational efficiency and power consumption are improved, but signal-to-noise ratio deteriorates due to PVT variations
Solution Approach 1:
The patent divides the analog multiplication operation into two separate stages: first computing a partial sum using only the most significant bits (MSBs) of the multiplier, then computing a second partial sum using the least significant bits (LSBs). This segmentation allows each stage to operate with reduced noise accumulation, as the MSB stage captures the dominant signal components while the LSB stage captures finer details with controlled noise. The final result is obtained by combining these two partial sums, achieving high precision without the noise accumulation that would occur in a single-stage analog multiplication.
2Measurement precision
If more bits are used in digital multiplier to improve precision, then measurement precision is improved, but device complexity increases
Solution Approach 1:
Instead of implementing a single complex high-bit digital multiplier, the patent segments the multiplication into two simpler operations: one using only MSBs and another using only LSBs. Each operation uses a lower-bit multiplier, reducing the complexity of individual multiplier circuits. The overall precision is maintained by combining the results of these two simpler operations, effectively trading circuit complexity for a multi-step computational approach.
Solution Approach 2:
The patent computes the multiplication result in two separate partial sums rather than attempting to compute the full precision result in a single operation. The first partial sum uses a subset of the multiplier bits (MSBs), and the second partial sum uses the remaining bits (LSBs). This partial action approach allows each computational step to be simpler while the combination of partial results achieves the desired overall precision.
Data Source
AI summary
A mixed analog/digital in-memory computing device implements matrix vector multiplication with reduced noise for use by a deep neural network (DNN). For each row of a cross-bar array a digital multiplier is split into a least significant (LS) portion and a most significant (MS) portion of different sizes that are preloaded into two cells on one row and two different columns of the cross-bar array. An input activation (IA) value is driven onto input conductors of each row and an analog-to-digital converter (ADC) converts output signals from the two columns as a MS partial sum and a LS partial sum. A gain is applied to the MS partial sum and added to the LS partial sum to form a resulting value for one node of the DNN.