Crossbar Memory Selection Layout for Stable Writing Current
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Solution Overview
Problem
In crossbar circuits with a large number of resistance variable elements, the use of unipolar transistors for selecting rows and columns leads to issues with source potential floating, resulting in decreased writing current and deteriorated current characteristics, which can be mitigated by increasing gate width, but this worsens layout efficiency.
Innovation Solution
A semiconductor device configuration that includes variable-resistance type switches and selection transistors with well terminal connection lines, where the well terminal connection lines are electrically insulated, allowing for improved control of source potential and increased writing current without expanding layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If unipolar transistors are used for selecting rows and columns in crossbar circuits, then layout constraints are satisfied, but source potential floats causing decreased writing current and deteriorated current characteristics
Solution Approach 1:
The selection transistor is divided into two independent gates (first gate and second gate) that can be controlled separately. This segmentation allows independent optimization of each gate's function: the first gate controls row selection while the second gate controls column selection, enabling precise control of the source potential without compromising layout efficiency
Solution Approach 2:
The invention changes the control parameter from a single gate voltage to two independent gate voltages. By applying different voltages to the first and second gates, the source potential can be precisely regulated to prevent floating, thereby improving current characteristics while maintaining the same layout footprint
2Reliability
If gate width is increased to improve writing current, then current characteristics are improved, but layout area increases
Solution Approach 1:
Instead of increasing the overall transistor size, the invention segments the gate control into two independent gates. This allows the writing current to be enhanced through optimized gate voltage control rather than through physical size increase, thereby maintaining layout area efficiency while improving current characteristics
Solution Approach 2:
The invention changes from controlling current through physical dimension (gate width) to controlling current through electrical parameter (dual gate voltages). By adjusting the voltages applied to the first and second gates, the writing current can be optimized without increasing the transistor's physical footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration enhances current characteristics during writing and reading operations while maintaining efficient layout, preventing the decrease in writing current and improving overall performance.
Implementation Method 1
resistance variable elements employing movement of metal ions and electrochemical reaction within solid (hereinafter, also referred to as an 'ion conductor') in which ions can freely move responding to applying an electric field or the like
Implementation Method 2
Metal ions are supplied from the first electrode to the ion conductive layer. Metal ions are not supplied from the second electrode. The resistance variable elements disclosed in PTL1 and NPL1 change a resistance value of an ion conductor responding to a change in polarity of an applied voltage
Data Source
AI summary
In order to eliminate an increase in the source potential of a transistor selected during writing or reading, this semiconductor device is equipped with: a variable-resistance type first switch having a first terminal and a second terminal; a variable-resistance type second switch having a third terminal and a fourth terminal, the third terminal being connected to the second terminal to form an intermediate node; first wiring connected to the first terminal; second wiring connected to the fourth terminal and, in a planar view, extending in a direction crossing the first wiring; a first selection transistor connected to the first wiring; a second selection transistor connected to the second wiring; a first well terminal connection line to which a well terminal of the first selection transistor is connected; and a second well terminal connection line to which a well terminal of the second selection transistor is connected.