Buffered Crossbar Switch Clock Domain Power Optimization
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Solution Overview
Problem
Power consumption remains a concern in the design of buffered crossbar switches, despite existing techniques such as disabling inactive ports and low-power design synthesis, as they do not adequately reduce energy usage while maintaining performance.
Innovation Solution
The implementation of a packet switch with clock modules generating output clock signals for input ports, allowing crosspoints to store and route data units across different clock domains, enabling users to select frequencies to minimize power consumption while optimizing performance by configuring output bandwidths and frequencies based on input bandwidths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of output clock signals of input ports is increased to improve data routing performance, then the packet switch performance is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment where each input port can independently configure its output clock signal frequency based on actual traffic conditions and performance requirements. This allows the system to adaptively optimize between power consumption and performance rather than operating at fixed high frequency
Solution Approach 2:
The patent changes the frequency parameter of output clock signals dynamically. By allowing users to select different frequencies for output clock signals of input ports, the system can adjust the operating parameters to minimize power consumption while maintaining acceptable performance levels
2Use of energy by moving object
If additional clock generation circuitry is added to enable flexible bandwidth configuration, then power consumption can be optimized, but device complexity increases
Solution Approach 1:
The patent makes the existing clock modules serve multiple functions: they generate output clock signals for input ports, enable flexible bandwidth configuration, and support power consumption optimization. This eliminates the need for separate dedicated circuitry for these functions
Solution Approach 2:
The system uses its existing clock modules to generate the necessary output clock signals without requiring external or additional clock generation circuitry. The clock modules self-configure to provide the required frequencies based on user selections for bandwidth and power optimization
Data Source
AI summary
A communication system that includes a packet switch having a buffered crossbar for routing data packets from input ports to output ports of the packet switch. The buffered crossbar stores a data packet received from an input port based on a clock signal of a clock domain and sends the data packet to an output port of the packet switch based on a clock signal of another clock domain. In this way, the buffered crossbar functions as a clock domain boundary between the input port and the output port. Moreover, the frequency of one or both of the clock signals may be selected to minimize power consumption in the packet switch or to select a tradeoff between power consumption and performance of the packet switch.