Crossbar Switch Dual Pickers Command Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current crossbar switch architectures in multi-core processors are inefficient due to insufficient data bandwidth, undersized packet buffers, and imperfect scheduling, leading to dead slots on routing buses and reduced performance.
Innovation Solution
The implementation of a crossbar switch with primary and secondary pickers, dedicated command and data buses, and increased packet buffer sizes to enhance bandwidth and efficiency by scheduling two commands per clock cycle and maintaining order in command routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single picker is used to schedule commands in the crossbar switch, then the device complexity is low, but the productivity is limited to one command per clock cycle
Solution Approach 1:
The crossbar switch command scheduler is segmented into a primary picker and a secondary picker, allowing independent parallel operation. The primary picker handles first-priority commands while the secondary picker handles second-priority commands, enabling two commands to be scheduled per clock cycle and doubling the throughput capability
Solution Approach 2:
The picker architecture is extended from a single-dimensional selection to a two-dimensional hierarchy with primary and secondary pickers operating at different priority levels. This dimensional expansion allows the system to process multiple command streams simultaneously without increasing physical space requirements
2Quantity of substance
If shared command/data buses are used, then the device complexity is low, but the data bandwidth is insufficient and dead slots occur
Solution Approach 1:
The shared bus architecture is segmented into dedicated command buses and dedicated data buses. Command packets traverse dedicated command buses while data packets traverse dedicated data buses, eliminating contention between command and data traffic and preventing dead slots where buses remain idle
Solution Approach 2:
The system merges dedicated command buses and dedicated data buses into a unified crossbar fabric, allowing simultaneous command and data transmission through the same physical switch matrix without interference, thereby maximizing bandwidth utilization
3Reliability
If undersized packet buffers are used, then the device complexity is low, but the reliability of command routing is reduced
Solution Approach 1:
Packet buffers are segmented into separate command packet buffers and data packet buffers, with dedicated buffers for each source-destination pair. This segmentation ensures that command packets and data packets are buffered independently, preventing overflow and loss while maintaining routing reliability
Solution Approach 2:
Packet buffers are pre-configured with sufficient depth to accommodate peak traffic loads before commands are fully processed. This preliminary buffering capacity ensures that no commands are lost due to temporary congestion, maintaining reliable routing under varying load conditions
Data Source
AI summary
A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.