Crossbar Molecular Synthesis Array for Dense Selective Addressing
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Solution Overview
Problem
Existing molecular synthesis arrays face challenges in achieving high density and selective addressing of synthesis locations due to the complexity of electrode routing and limited density, which complicates scaling and increases the risk of crosstalk between neighboring synthesis locations.
Innovation Solution
A molecular synthesis array with a crossbar structure comprising column and row lines, each synthesis cell having a lower and upper electrode separated by an insulating layer, and a select transistor, allowing for selective addressing and reduced crosstalk through a crossbar structure that reduces the number of necessary connections and utilizes self-capacitance for maintaining reaction conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If every electrode is addressed one-by-one with dedicated routing, then selective addressing of synthesis locations is achieved, but the area needed for routing increases and electrode density decreases
Solution Approach 1:
The patent transitions from one-dimensional linear addressing to two-dimensional crossbar addressing by introducing row lines and column lines that intersect to form synthesis locations. This allows any synthesis location to be addressed by the intersection of one row line and one column line, eliminating the need for dedicated routing paths and significantly reducing routing area while maintaining selective addressing capability.
2Quantity of substance
If the number of electrodes is increased to achieve high density, then synthesis capacity increases, but routing complexity increases and scalability becomes challenging
Solution Approach 1:
By organizing electrodes in a two-dimensional crossbar grid with N row lines and M column lines, the system can address N×M synthesis locations using only N+M connection lines. This dimensional reorganization reduces routing complexity from O(N×M) in a fully connected system to O(N+M) in the crossbar configuration, enabling scalable high-density arrays.
Solution Approach 2:
Each row line and column line serves multiple functions by participating in multiple synthesis locations through their intersections. A single row line can simultaneously or sequentially address multiple synthesis locations by combining with different column lines, making the routing infrastructure universal rather than dedicated to specific locations.
3Area of stationary object
If synthesis locations are placed closer together to increase density, then area efficiency improves, but crosstalk between neighboring locations increases
Solution Approach 1:
The patent introduces select transistors as intermediary switching elements between the crossbar lines and the synthesis locations. These transistors act as gates that can be opened or closed to control current flow to specific synthesis locations, preventing crosstalk by ensuring that only the intended location receives activation current even when lines are in close proximity.
Solution Approach 2:
The select transistor at each synthesis location provides localized control of electrical properties, allowing each location to be independently activated or deactivated. This local control mechanism ensures that electrical signals remain confined to their intended destinations, preventing harmful crosstalk effects even in high-density configurations where synthesis locations are closely spaced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-density synthesis arrays with reduced crosstalk and complexity, allowing for efficient, scalable, and time-multiplexed synthesis processes with improved area efficiency and reduced risk of cross-reaction interference.
Implementation Method 1
a select transistor having a first terminal, a second terminal and a gate terminal, the first and second terminals forming respective source/drain terminals of the select transistor, wherein the gate terminal is coupled to the row line, the first terminal is coupled to the column line, the second terminal is coupled to the lower electrode
Implementation Method 2
DNA chips may comprise arrays of electrodes providing electrochemically controlled in situ synthesis of different oligonucleotides at defined positions in the array
Implementation Method 3
utilizes self-capacitance for maintaining reaction conditions
Data Source
AI summary
According to an aspect of the present inventive concept there is provided a molecular synthesis array comprising: a substrate; an insulating layer (202) arranged on the substrate; a plurality of column lines (102) extending in parallel along a column direction of the molecular synthesis array (100), and a plurality of row lines (104) extending in parallel along a row direction of the molecular synthesis array (100), wherein the column lines (102) are vertically separated from the row lines (104) and extend transverse to the row lines (104); a plurality of synthesis cells (105), wherein each cell (200) is coupled to a respective pair of a column line and a row line and comprises: a lower electrode (226) and an upper electrode (206) vertically separated from each other and embedded in the insulating layer (202), a synthesis well (223) extending from an upper surface (225) of the insulating layer (202) to the lower electrode (226), through the insulating layer (202) and through the upper electrode (206), wherein the well (223) exposes a surface portion (214) of the upper electrode (206) and a surface portion (220) of the lower electrode (226), and a select transistor (106) having a first terminal (114a), a second terminal (114b) and a gate terminal (114c), the first and second terminals (114a, 114b) forming respective source/drain terminals of the select transistor (106), wherein the gate terminal (114c) is coupled to the row line, the first terminal (114a) is coupled to the column line, the second terminal (114b) is coupled to the lower electrode (226), and the upper electrode (206) is coupled to a reference voltage, or wherein the gate terminal (114c) is coupled to the row line, the first terminal (114a) is coupled to the column line, the second terminal (114b) is coupled to the upper electrode (206), and the lower electrode (226) is coupled to a reference voltage.