Crossed-Fin Transistor Structure for Low-Power Mobile Applications
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Solution Overview
Problem
Current semiconductor structures and fabrication processes are inadequate for the shrinking device size and high-performance, low-power mobile applications, necessitating new device structures and processes beyond three-dimensional FinFETs.
Innovation Solution
A semiconductor structure comprising a substrate with intersecting elongated n-type and p-type regions and a shared gate structure over their common area, along with a method of creating such structures using conventional processes, enabling efficient fabrication of crossed-fin structures for low-power applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FinFET structures are used, then fabrication processes are well-established, but device size cannot shrink further and performance for low-power applications is insufficient
Solution Approach 1:
The patent transitions from conventional planar or single-dimension FinFET structures to a two-dimensional crossed-fin configuration where fins extend in perpendicular directions (e.g., X and Y axes). This dimensional change increases the gate-controlled channel area without proportionally increasing the footprint, thereby improving device performance and drive current for low-power applications while managing structural complexity through symmetric geometry.
2Area of moving object
If device size is reduced to meet mobile application requirements, then integration density increases, but conventional structures become inadequate and require new device architectures
Solution Approach 1:
By implementing crossed-fins extending in perpendicular directions with a shared gate, the patent achieves higher integration density within a reduced footprint. The multi-dimensional configuration allows the device to maintain electrical performance while occupying less area, making it suitable for mobile applications requiring high density.
Solution Approach 2:
The crossed-fin structure with shared gate serves multiple functions: it provides enhanced drive current through increased channel area, achieves low-power operation through improved gate control, and enables scalable integration. The symmetric geometry allows the same structure to function effectively across different device sizes and application requirements.
3Power
If new device structures beyond FinFETs are implemented, then performance for low-power applications improves, but fabrication processes become more complex
Solution Approach 1:
The crossed-fin structure can be fabricated using extended conventional processes by forming fins in perpendicular directions through sequential epitaxial growth and etching steps. The shared gate is formed over the intersection region using standard gate deposition techniques. This approach achieves improved power efficiency through enhanced gate control and increased channel area while relying on well-established fabrication methods, thereby maintaining ease of manufacture.
Data Source
AI summary
A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.