Crossed Matrix Parity for Memory Error Correction
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Solution Overview
Problem
Memory devices experience intermittent failures due to repeated accesses, leading to errors in data storage, which existing error correction methods struggle to manage effectively, especially as the number of errors exceeds correctable limits, causing reliability issues.
Innovation Solution
Implementing crossed matrix parity by generating and analyzing parity data for both rows and columns of memory cells, allowing a host to pinpoint error locations and perform error correction, thereby maintaining error rates below threshold levels without altering the memory device hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used, then simple error cases can be corrected, but the method fails when the number of errors exceeds correctable limits
Solution Approach 1:
The patent segments the memory array into multiple groups, with each group having its own parity bits. This division allows independent error correction for each segment, enabling the system to handle errors that would otherwise exceed the correction capability of a single traditional code block.
Solution Approach 2:
The patent introduces a two-dimensional parity structure by organizing parity bits both horizontally (row parity) and vertically (column parity). This dimensional transformation enables the system to detect and correct errors by analyzing parity failures in multiple directions, significantly enhancing error handling capability beyond traditional single-dimension methods.
2Measurement precision
If more parity data is generated for better error detection, then error locations can be pinpointed accurately, but the processing complexity and time increase
Solution Approach 1:
By dividing the memory array into smaller groups with individual parity bits, the patent reduces the complexity of parity calculation and analysis for each segment. This segmentation allows accurate error location detection within manageable units rather than requiring complex processing of the entire large array.
Solution Approach 2:
The patent generates parity data for all groups and performs comprehensive parity checks on both rows and columns. This excessive action of creating multiple parity layers ensures complete error location precision, as the intersection of failed row and column parities uniquely identifies error positions.
Data Source
AI summary
Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first group of sets of parity data that each protect data stored in a row of memory cells of an array is generated. Further, a second group of sets of parity data that each protect data stored in a column of memory cells of an array is generated. The first set of parity data and the second set of parity data is sent to a host for further ECC processing. The host provides ECC data to the memory device based on the first set of parity data and the second set of parity data. The memory device repairs memory cells or retires memory cells based on the provided ECC data.