Crossed Matrix Parity for NAND Memory Error Localization
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Solution Overview
Problem
Memory devices face challenges in efficiently managing errors due to repeated access, leading to intermittent failures and increased bit error rates, which existing error correction methods struggle to address effectively, especially in non-volatile memory devices like NAND flash.
Innovation Solution
Implementing crossed matrix parity by writing parity data to both rows and columns of memory cells, allowing for error correction by pinpointing error locations and retiring weak rows to maintain error rates below threshold levels, thereby enhancing reliability and reducing bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction methods are used in non-volatile memory devices, then implementation is simpler, but bit error rates increase and reliability deteriorates due to repeated access
Solution Approach 1:
The patent divides the error correction approach into two segments: crossed matrix parity for locating errors and ECC for correcting errors. This segmentation allows each component to specialize - parity handles error location efficiently while ECC handles correction, resolving the contradiction between reliability improvement and complexity management
Solution Approach 2:
The patent introduces a second dimension of parity checks by implementing both row parity and column parity in a crossed matrix structure. This two-dimensional approach enables precise error location at the intersection of failed parity checks, improving reliability without proportionally increasing complexity compared to single-dimensional methods
2Reliability
If more extensive error correction is implemented, then bit error rates reduce, but device complexity and processing overhead increase
Solution Approach 1:
The patent performs preliminary error location using crossed matrix parity before applying ECC correction. By pre-identifying error locations through the parity matrix, the system prepares the data in an optimized state for correction, reducing the processing burden during the actual ECC operation and maintaining productivity while improving data integrity
Solution Approach 2:
The patent replaces brute-force exhaustive error checking with a more efficient parity matrix system. Instead of checking all possible error combinations, the crossed matrix parity provides a mathematical framework that quickly identifies error locations, substituting complex mechanical searching with elegant mathematical computation
3Reliability
If weak rows are not retired, then memory capacity is maximized, but error rates exceed threshold and uncorrectable errors occur
Solution Approach 1:
The patent implements a feedback mechanism where parity check results inform retirement decisions. When crossed matrix parity identifies that a row contains errors exceeding the correctable threshold, this feedback triggers the retirement of that row, preventing uncorrectable errors while maintaining reliability for the remaining usable memory
Solution Approach 2:
The patent applies the principle of discarding weak rows that cannot be reliably corrected, while recovering and maintaining the health of the overall memory system. By selectively retiring only the weakest rows rather than entire memory arrays, the system preserves maximum usable capacity while ensuring reliability thresholds are maintained
Data Source
AI summary
Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first plurality of sets of parity data to memory cells in the array that each protect data stored in a row of memory cells of the array can be written to the array. Further, a second plurality of sets of parity data to memory cells in the array that each protect data stored in a column of memory cells of the array can be written to the array. The first plurality of sets of parity data and the second plurality of sets of parity data can be sent to a processor for further ECC processing. Error correction data can be received from a processor that indicates a cluster of data that includes a threshold quantity of errors. An error correction can be performed on the cluster of data.