Crossed Nanosheet Transistor Stacks for Non-Overlapping Source/Drain Contacts
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Solution Overview
Problem
Current semiconductor devices with multiple nanosheet layers face challenges in reducing transistor size and forming source/drain contact structures due to vertical overlap of source/drain regions, which complicates manufacturing and increases parasitic capacitance.
Innovation Solution
A multi-stack nanosheet structure is developed with different channel directions for each transistor stack, allowing source/drain regions to be formed without vertical overlap, enabling simpler contact structure formation and reduced parasitic capacitance by having source/drain contact structures land on top surfaces rather than side surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple nanosheet layers are vertically stacked in overlapping manner, then device density is increased, but source/drain regions vertically overlap complicating manufacturing and increasing parasitic capacitance
Solution Approach 1:
The patent introduces different channel directions (first channel length direction vs. second channel length direction) for upper and lower nanosheet stacks, effectively using spatial orientation in another dimension to separate source/drain regions vertically. This dimensional change allows high device density through vertical stacking while avoiding the parasitic capacitance and manufacturing complexity caused by vertical overlap of source/drain regions.
2Reliability
If source/drain contact structures are formed to access vertically overlapping source/drain regions, then electrical connection is achieved, but manufacturing complexity and parasitic capacitance increase
Solution Approach 1:
The patent extracts the source/drain regions from their vertically overlapping positions by orienting channel structures in different directions. This separation removes the harmful vertical overlap, allowing source/drain contact structures to be formed more easily without the need to navigate through overlapping regions, thereby reducing manufacturing complexity while maintaining reliable electrical connections.
3Length of moving object
If transistor size is reduced, then device integration is improved, but technology limits are reached even with multiple channel layers
Solution Approach 1:
Instead of further reducing transistor size in the planar dimension which has reached technology limits, the patent utilizes vertical stacking with different channel directions to achieve higher integration. This approach transitions from two-dimensional scaling to three-dimensional architecture, allowing continued miniaturization and increased device integration without being constrained by planar manufacturing precision limits.
Data Source
AI summary
A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region.