Crosshair Memory Arrays With Segmented Wordlines
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Solution Overview
Problem
Current finFET devices face challenges in integrating them into highly integrated memory and circuitry applications, requiring improved architectures and fabrication methods to enhance performance and efficiency.
Innovation Solution
The development of memory device architectures featuring crosshair memory cells with semiconductor fins, wordline trunk and branch regions, and digit lines, where wordline branch regions overlap channel regions to selectively control current flow, and the use of specific semiconductor materials and fabrication processes to form these structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If finFET devices are incorporated into highly integrated memory arrays, then memory density and integration level are improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The wordline structure is segmented into trunk regions and branch regions, where trunk regions extend in a first direction and branch regions extend in a second direction. This segmentation allows for systematic organization of complex interconnects, enabling higher memory density while managing fabrication complexity through modular design approaches.
Solution Approach 2:
The patent utilizes three-dimensional finFET structures with vertical channel regions extending perpendicular to the substrate, transitioning from planar to vertical transistor architectures. This dimensional change enables increased device density without proportionally increasing planar footprint, addressing the memory density requirement while managing fabrication complexity through established vertical processing techniques.
2Measurement precision
If wordline branch regions overlap channel regions to control current flow, then memory cell addressing precision is improved, but manufacturing precision requirements increase
Solution Approach 1:
Gate dielectric material is introduced as an intermediary layer between the wordline branch regions and the channel regions. This dielectric layer provides electrical isolation while allowing the wordline branches to overlap and control the channel, achieving precise memory cell addressing without requiring direct contact alignment, thereby reducing manufacturing precision requirements.
Solution Approach 2:
The gate dielectric material is formed prior to depositing the wordline branch regions, establishing a predefined interface that simplifies subsequent alignment processes. This preliminary action ensures that the overlapping structure achieves the required addressing precision while reducing the stringency of manufacturing alignment tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables improved control over current flow and memory cell addressing, enhancing the integration and performance of finFET devices in highly integrated memory arrays, allowing for more efficient operation and unique addressing of memory cells.
Implementation Method 1
gate material is spaced from the sidewall by gate dielectric material. A pair of source/drain regions is provided within the fin, and a channel region extends between the source/drain regions. In operation, the gate is utilized to selectively control current flow within the channel region.
Data Source
AI summary
Some embodiments include a memory array having memory cells arranged in rows and columns. The rows extend along a first direction and the columns extend along a second direction, with an angle between the first and second directions being less than 90°. Wordline trunk regions extend across the array and along a third direction substantially orthogonal to the second direction of the columns. Wordline branch regions extend from the wordline trunk regions and along the first direction. Semiconductor-material fins are along the rows. Each semiconductor-material fin has a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. Each channel region is overlapped by a wordline branch. Digit lines extend along the columns and are electrically coupled with the second source/drain regions. Charge-storage devices are electrically coupled with the first source/drain regions.