Crosslink Fin Layout for VFETs With Higher Weff and Lower Capacitance
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Solution Overview
Problem
The challenge in fabricating vertical field-effect transistors (VFETs) lies in scaling fin width and pitch due to quantum effects, patterning process limitations, and high parasitic capacitance between source/drain contacts and gate, which restricts the flexibility and effective width (Weff) of fin structures.
Innovation Solution
The method involves forming crosslink fin structures by creating a combination of first and second mandrels with sidewall image transfer spacers, allowing for the definition of a crosslink fin pattern that reduces parasitic capacitance and enhances Weff through a flexible design, enabling the simultaneous fabrication of crosslink and single fin structures with desirable parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If fin width and fin pitch are scaled down to increase device density, then device footprint is reduced, but quantum effects and patterning process limitations worsen
Solution Approach 1:
The patent transitions from planar fin structures to vertical fin structures that extend in the third dimension (vertical direction perpendicular to substrate). This dimensional change allows increased effective width without further lateral scaling, avoiding the quantum effects and patterning limitations that constrain continued reduction of fin width and pitch in the planar domain.
Solution Approach 2:
The patent introduces flexible fin structures with configurable parameters including number of fins, fin width, fin pitch, and vertical height. This dynamic design allows optimization of device characteristics for different applications, enabling the system to adapt to various performance requirements rather than being constrained by fixed geometric scaling rules.
2Quantity of substance
If conventional fin structures (C-shaped, Pi-shaped, U-shaped) are used to increase effective width, then Weff is improved, but parasitic capacitance between source/drain contacts and gate increases
Solution Approach 1:
The patent employs asymmetric fin structures where fins have different widths, heights, or spacing configurations. This asymmetry allows optimization of the electric field distribution and current flow paths, reducing the overlap between source/drain depletion regions and the gate, thereby minimizing parasitic capacitance while maintaining high effective width.
Solution Approach 2:
The patent applies different geometric characteristics to different regions of the fin structure. For example, fins may have varying widths along their length or different spacing in different areas, allowing local optimization of electrical characteristics to reduce parasitic effects in critical regions while maintaining overall high effective width.
3Ease of manufacture
If fin structures with fixed geometries are implemented, then manufacturing is simplified, but design flexibility is reduced
Solution Approach 1:
The patent creates a universal fin structure platform that can be configured for multiple different applications and performance requirements. The same basic vertical fin architecture can be adapted with different numbers of fins, widths, pitches, and heights to serve various device needs, eliminating the requirement for entirely different structure types for different applications.
Solution Approach 2:
The patent establishes a pre-configurable fin structure framework during the design stage where parameters such as fin count, dimensions, and spacing can be predetermined and optimized. This preliminary configuration allows the same fabrication process to produce多种 variants, balancing manufacturing simplicity with design flexibility.
Data Source
AI summary
A method of forming a semiconductor structure includes forming a first array of mandrels on a hardmask layer disposed on an uppermost surface of a semiconductor substrate. First sidewall image transfer spacers are formed on opposing longitudinal sidewalls of each mandrel in the first array of mandrels. A second array of mandrels is formed on the hardmask layer. Each mandrel in the second array of mandrels is laterally separated from each mandrel in the first array of mandrels by the first sidewall image transfer spacers. Second sidewall image transfer spacers are formed on opposing transversal sidewalls of the first array of mandrels and the second array of mandrels. Portions of the second sidewall image transfer spacers are selectively removed to define a crosslink fin pattern to be transferred to the semiconductor substrate.