Cross-Point Clock Synchronization for Multi-FPGA Circuit Emulators
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FPGA technology lacks the logical capacity to prototype the entirety of a single ASIC within a single device, necessitating the distribution and synchronization of clocks across multiple FPGAs, which poses challenges in maintaining synchronized operations across different clock frequencies and phases.
Innovation Solution
A system utilizing non-blocking cross-point switches and buffering devices to synchronize clock signals across multiple FPGAs, allowing for the operation of FPGAs at different frequencies and supporting multiple independent circuit designs by distributing and synchronizing clock inputs through a network of global and master Gateway Interface Boards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple FPGAs are used to implement a large circuit design, then the logical capacity is sufficient to prototype the entire ASIC, but clock synchronization becomes difficult to maintain across different frequencies and phases
Solution Approach 1:
The system divides the clock distribution function into multiple independent buffering devices, each responsible for a specific clock output. This segmentation allows each buffer to independently manage its clock signal while contributing to the overall synchronization of the multi-FPGA system, resolving the contradiction between increased logical capacity and clock synchronization reliability.
2Device complexity
If a single FPGA is used, then clock synchronization is simple, but the logical capacity is insufficient to implement the entire circuit design
Solution Approach 1:
The patent combines multiple buffering devices into a unified clock distribution system where each buffer receives inputs from a cross-point switch and outputs synchronized clock signals to FPGAs. This merging approach maintains relative simplicity in the overall system architecture while enabling the distributed system to achieve the total logical capacity needed for large circuit designs.
3Adaptability or versatility
If FPGAs operate at different frequencies, then each can be optimized for its specific function, but maintaining phase synchronization across all FPGAs becomes challenging
Solution Approach 1:
Each buffering device is configured with specific input selections from the cross-point switch, allowing local optimization for different frequency requirements while maintaining global phase synchronization. The cross-point switch enables each buffer to select appropriate clock inputs based on the specific frequency needs of connected FPGAs, resolving the contradiction between frequency flexibility and phase synchronization precision.
Data Source
AI summary
A system includes a first cross-point switch receiving a first plurality of clock inputs and outputting a first plurality of clock outputs, a first plurality of buffering devices receiving the first plurality of clock outputs and outputting a first plurality of buffered clock signals synchronized with each other, a first plurality of connectors receiving the first plurality of buffered clock signals and outputting a plurality of blade signals to a plurality of blades. Each blade includes a plurality of programmable logic devices, an operation of which is synchronized based on the first plurality of clock inputs. Each blade includes a second cross-point switch to receive a blade signal of the plurality of blade signals. The second cross-point switch outputs a second plurality of clock outputs based on the received blade signal, and the second plurality of clock outputs are provided to the programmable logic devices.