Crosspoint Fuse Array Layout for Dense OTP Memory Programming
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Solution Overview
Problem
One-time programmable memory in integrated circuits faces challenges in increasing storage capacity while minimizing semiconductor area and improving programming procedures, with existing technologies struggling to achieve precise control over fuse impedance and efficient use of circuitry.
Innovation Solution
The implementation of a compact fuse array with a crosspoint architecture that reduces the number of conductors and devices in each bit cell, using selected voltages on wordlines and bitlines for programming and reading, allowing for precise control over fuse impedance and deterministic electrical behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the storage capacity of one time programmable memory is increased, then the customization capability of IC is improved, but the semiconductor area required increases
Solution Approach 1:
The patent combines multiple functions into the crosspoint architecture: storage elements are formed at intersections of bitlines and wordlines, eliminating the need for separate address decode circuitry and reducing overall area. The same array structure serves both storage and addressing functions, allowing increased capacity without proportional area increase.
Solution Approach 2:
The patent transitions from a linear or hierarchical memory organization to a two-dimensional crosspoint array. By arranging storage elements at the intersections of bitlines and wordlines in a grid structure, the memory achieves higher density and capacity while minimizing the semiconductor footprint through spatial efficiency.
2Ease of manufacture
If conventional fuse array architecture is used, then the implementation is simple, but the manufacturing precision and control over fuse impedance are insufficient
Solution Approach 1:
The patent applies controlled voltage parameters during programming to precisely regulate fuse impedance. By adjusting the magnitude and duration of voltages applied to selected bitlines and wordlines, the system achieves deterministic control over fuse resistance values, enabling precise impedance matching and improved manufacturing precision without complicating the basic array structure.
3Adaptability or versatility
If more conductors and devices are added to each bit cell, then the functionality is improved, but the semiconductor area and device complexity increase
Solution Approach 1:
The crosspoint architecture enables each intersection of bitline and wordline to serve multiple purposes: storing data, addressing memory locations, and controlling fuse programming. The same conductors used for addressing also serve as data lines, eliminating the need for separate control lines and reducing overall device complexity while maintaining full functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more efficient use of semiconductor area, reduced complexity in manufacturing, and improved precision in programming and reading operations, leading to a more deterministic electrical behavior of the memory array.
Implementation Method 1
a transistor having a control electrode, a first current electrode, and a second current electrode, wherein the control electrode of the transistor is coupled to the first current electrode of said transistor and to the first terminal of the fuse
Implementation Method 2
using selected voltages on wordlines and bitlines for programming and reading, allowing for precise control over fuse impedance and deterministic electrical behavior
Data Source
AI summary
The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses.