Cross-Point Resistive Memory Write Mapping for Uniform Bit Error Rates

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Solution Overview

Problem

Existing resistive memory devices face issues with non-uniform bit error rates due to differences in characteristics among layers, leading to increased complexity in error correction algorithms and resource utilization.

Innovation Solution

A method of operating a resistive memory system that involves converting a write request into sub-region data and distributing these data across multiple layers, ensuring uniform bit error rates by assigning sub-region data to different layers based on error correction units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is stored in multiple layers without distribution, then storage capacity is increased, but bit error rates become non-uniform across layers

Engineering Contradiction:

Improvestorage capacityVSAvoiduniformity of bit error rates

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent divides data into multiple sub-region data segments and distributes them across different layers. Each layer stores a portion of the total data, and the distribution is designed so that bit errors are uniformly distributed across all layers. This segmentation approach maintains high storage capacity while ensuring uniform reliability characteristics.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different storage strategies to different layers based on their specific characteristics. By analyzing and compensating for layer-specific variations, the system achieves uniform bit error rates across layers with different inherent qualities, rather than treating all layers identically.

Inventive Principle:

Principle #3Local quality

2Reliability

If layer-specific error correction is implemented, then data reliability is improved, but algorithm complexity and resource utilization increase

Engineering Contradiction:

Improvedata reliabilityVSAvoiderror correction algorithm complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent creates uniform bit error rate characteristics across all layers through strategic data distribution. This homogenization of error characteristics allows the use of simplified, uniform error correction algorithms rather than complex layer-specific algorithms, reducing overall system complexity while maintaining high reliability.

Inventive Principle:

Principle #33Homogeneity

Data Source

PatentUSRE50519E1Cross-point memory device and method for converting and storing write data and associated parity to achieve uniform bit error rates

Publication Date: 2025.08.05 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.