Crosspoint Memory Array Bit Line Contact Overlap
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the integration of memory devices with a crosspoint structure increases, electrical characteristic differences among individual memory units occur due to variations in their positions, leading to inconsistent performance and reliability issues.
Innovation Solution
A memory device design with a crosspoint array structure where first and second memory cells, each comprising a memory unit and a switching unit, are arranged symmetrically with respect to a common bit line, ensuring identical current flow directions and reducing electrical characteristic differences by using vertically overlapping bit line contacts for uniform operating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of memory devices is increased, then the memory device becomes more compact and highly integrated, but electrical characteristic differences among individual memory units occur due to position variations
Solution Approach 1:
The patent introduces asymmetric dummy structures (dummy bit lines or dummy word lines) adjacent to actual memory cells. These dummy structures have different configurations from the actual memory cells, creating intentional asymmetry in the array. This asymmetric design compensates for position-dependent electrical characteristic variations by providing reference structures that help equalize the electrical environment across different locations in the high-density memory array.
Solution Approach 2:
The patent modifies physical parameters of the memory structure, specifically by introducing dummy bit lines or word lines with controlled dimensions and positions. By changing the geometric parameters and electrical characteristics of these dummy structures, the patent adjusts the overall electrical field distribution and current flow patterns to compensate for position-dependent variations in highly integrated memory arrays.
2Area of stationary object
If memory cells are arranged in a crosspoint array structure, then the memory device achieves high integration density, but electrical characteristic differences occur among memory units at different positions
Solution Approach 1:
The patent introduces dummy bit lines or dummy word lines as intermediary structures between the actual memory cells and the external circuitry. These intermediary dummy structures act as buffers that mediate the electrical interactions in the array, compensating for position-dependent variations by providing a standardized reference environment that equalizes operating characteristics across all memory cells in the dense crosspoint array.
Solution Approach 2:
The patent uses dummy structures to create equipotential reference regions throughout the memory array. By strategically placing dummy bit lines or word lines, the patent establishes uniform electrical potential distributions that compensate for position-dependent variations, ensuring that memory cells at different locations experience similar electrical conditions and thus maintain consistent operating characteristics.
Data Source
AI summary
A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.