Crosspoint Memory Architecture With Direct Via Access for Low Resistance

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Solution Overview

Problem

In memory devices, thermal barrier materials introduce resistance issues when used between electrodes and access lines, reducing current delivery due to signal passage through the material twice, which affects the programming and reading of memory cells.

Innovation Solution

Depositing the thermal barrier material before the array termination etch, allowing the conductive via to interface directly with the access line, and using a liner and cap material to mitigate manufacturing damage and resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If thermal barrier material is deposited after array termination etch, then thermal protection is provided, but resistance increases and current delivery is reduced

Engineering Contradiction:
Improvethermal protectionVSAvoidcurrent delivery
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The thermal barrier material is deposited before the array termination etch process, allowing the conductive via to interface directly with the access line without the thermal barrier material in between. This preliminary action prevents the resistance issue while still providing thermal protection where needed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the thermal barrier material deposition process from the via formation process, creating distinct regions where the thermal barrier is present (for thermal protection) and absent (for low-resistance electrical connection). This segmentation allows both thermal protection and low resistance to coexist in different parts of the structure.

Inventive Principle:
Principle #1Segmentation

2Temperature

If thermal barrier material is present between conductive via and access line, then thermal properties are improved, but resistance increases

Engineering Contradiction:
Improvethermal propertiesVSAvoidresistance control
Core Design Contradiction:
TemperatureVSManufacturing precision

Solution Approach 1:

The thermal barrier material is deposited before the array termination etch that creates the conductive via. This timing ensures that the via interface with the access line is not compromised by the thermal barrier material, maintaining manufacturing precision for resistance control.

Inventive Principle:
Principle #10Preliminary action

3Temperature

If signal passes through thermal barrier material twice, then thermal protection is enhanced, but current delivery is reduced

Engineering Contradiction:
Improvethermal protectionVSAvoidcurrent delivery
Core Design Contradiction:
TemperatureVSUse of energy by moving object

Solution Approach 1:

The patent extracts the thermal barrier material from the signal path between the conductive via and the access line. By removing the thermal barrier material from this specific interface region, current delivery is improved while thermal protection is maintained in other regions where the barrier material remains.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11882774B2Low resistance crosspoint architecture
Publication Date: 2024.01.23 MICRON TECHNOLOGY INC
  • US11882774B2 patent drawing
  • US11882774B2 patent drawing
  • US11882774B2 patent drawing

AI summary

Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.