Crosspoint Memory Parallel Read Architecture for Bandwidth Optimization

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Solution Overview

Problem

The bandwidth in reading crosspoint arrays of memory cells is relatively low due to the need to read one memory cell at a time, which limits the efficiency of data retrieval operations in semiconductor memory devices.

Innovation Solution

Implementing a method to read multiple crosspoint arrays in parallel, where one memory cell per array is read at a time, by selecting a row and then reading memory cells in different columns while maintaining the same row selection, and organizing crosspoint arrays into groups or sets to allow overlapping read operations, thereby reducing the time required for data retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple crosspoint arrays are read in parallel, then bandwidth and read speed are improved, but device complexity and control difficulty increase

Engineering Contradiction:
ImprovebandwidthVSAvoidcontrol complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The memory system is segmented into multiple independent crosspoint arrays (XPA0-X3) that can be accessed simultaneously. Each array has its own decoder and control logic, allowing parallel read operations while maintaining individual control. This segmentation enables bandwidth multiplication without requiring a completely new control architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from sequential single-array access to multi-dimensional parallel access by organizing memory into multiple arrays that can be addressed simultaneously through different column decoders. This adds a spatial dimension to the access pattern, enabling multiple read operations to occur in the same time cycle across different arrays.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Loss of time

If crosspoint arrays are organized into groups or sets, then read time is reduced through overlapping operations, but device complexity increases

Engineering Contradiction:
Improveread timeVSAvoidarchitecture complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system performs preliminary row selection and maintains it across multiple column read operations. By pre-selecting the row once and keeping it active, the system enables sequential column reads without repeated row setup overhead. This preliminary action reduces the total read time for multi-column operations within the same row.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The row selection is maintained continuously across multiple column read operations rather than being re-established for each read. This continuous row activation allows back-to-back column reads to occur without interruption or setup delay, maximizing the utilization of the selected row and reducing overall access time.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If one memory cell is read at a time, then device complexity is minimized, but bandwidth and efficiency are limited

Engineering Contradiction:
Improvedata retrieval efficiencyVSAvoidcontrol architecture
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple crosspoint arrays are merged into a single memory system that shares common control logic and output buffering. The arrays are combined at the decoder and sense amplifier levels, allowing simultaneous read operations to be coordinated through unified control signals while maintaining individual array independence for parallel access.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The control architecture is designed with universal decoders and control logic that can address and control multiple crosspoint arrays through the same interface. The row and column decoders are configured to work across all arrays, providing a unified control mechanism that manages parallel operations without requiring separate dedicated control paths for each array.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11099784B2Crosspoint memory architecture for high bandwidth operation with small page buffer
Publication Date: 2021.08.24 SANDISK TECHNOLOGIES LLC
  • US11099784B2 patent drawing
  • US11099784B2 patent drawing
  • US11099784B2 patent drawing

AI summary

Apparatuses and techniques are described for reading crosspoint arrays of memory cells with high bandwidth and a relatively small page buffer. Multiple crosspoint arrays (XPAs) are read in parallel, with one memory cell per XPA being read, in a bank of XPAs. To reduce the read time, a row can be selected for the XPAs, after which memory cells in different columns are read, one column at a time, while the same row is selected. This avoids the need to transmit commands and a row address for re-selecting the row in each successive read operation. The XPAs may be ungrouped, or one XPA may be accessible at a time in a group. In one option, the XPAs are arranged in sets, either individually or in groups, and one set is accessible at a time.