Crosspoint Memory Selection Scheme for Transient Current Reduction

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Solution Overview

Problem

Traditional memory devices face scaling limitations and energy efficiency issues, leading to reliability and performance problems such as read-disturb and write-endurance issues in crosspoint memory cells due to parasitic transient currents known as selection spikes.

Innovation Solution

A selection scheme that controls the ramp rate of the selection voltage waveform, slowly increasing the voltage until the memory cell thresholds and then reducing it to minimize additional transient current during read or write operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a voltage is applied to select a memory cell, then the memory cell can be accessed for read or write operations, but a parasitic transient current known as selection spike is generated causing read-disturb and write-endurance issues

Engineering Contradiction:
Improvememory cell selectionVSAvoidread-disturb and write-endurance performance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies a preliminary voltage ramp-up phase before the actual selection voltage is applied. The voltage is gradually increased from zero to the selection voltage level, allowing the memory cell to threshold smoothly without generating a sudden parasitic transient current spike. This preliminary action prepares the system state to avoid the harmful selection spike while maintaining reliable memory cell selection and access operations

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the selection voltage is increased to ensure reliable memory cell selection, then selection reliability improves, but the selection spike magnitude increases causing more severe read-disturb and write-endurance problems

Engineering Contradiction:
Improveselection reliabilityVSAvoidselection spike magnitude
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent transforms the static selection voltage application into a dynamic process by implementing a controlled voltage ramp-up waveform. Instead of applying a fixed voltage level abruptly, the voltage dynamically increases over time following a ramp profile, enabling the selection process to adapt to the memory cell's thresholding characteristics. This dynamic approach maintains selection reliability while minimizing the magnitude of parasitic transient currents throughout the selection process

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the effective bias required to select the memory cell, thereby minimizing selection spikes and improving read-disturb and write-endurance performance in crosspoint memory devices.

Implementation Method 1

until the memory cell thresholds

Methodology Applied
Scientific EffectThreshold voltage effect:

Data Source

PatentEP3886105B1Selection scheme for crosspoint memory
Publication Date: 2025.06.18 INTEL CORP
  • EP3886105B1 patent drawingFigure 1
  • EP3886105B1 patent drawingFigure 2A~2B
  • EP3886105B1 patent drawingFigure 3

AI summary

A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.