Crosspoint Memory Control Circuit Sneak Current Compensation

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Solution Overview

Problem

Conventional crosspoint nonvolatile memory devices face challenges in achieving stable forming due to sneak currents, which complicate the accurate detection of resistance values in variable resistance memory elements and hinder the reversible change of resistance states during the forming process.

Innovation Solution

A crosspoint nonvolatile memory device with a control circuit that adjusts the writing current or voltage and load current in proportion to the number of memory cells in the second resistance state, compensating for sneak currents by selecting appropriate load currents and writing pulses to exclude their influence during forming and reading operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a reading voltage is applied to detect the resistance value of a target memory cell in a crosspoint structure, then the resistance value can be detected, but a sneak current flows through other memory cells connected in parallel, preventing accurate detection

Engineering Contradiction:
Improvedetection accuracy of resistance valueVSAvoidsneak current
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and compensates for the sneak current component separately from the target current. By detecting the total current and subtracting the calculated sneak current (based on resistance values of other memory cells), the patent isolates the current through the target memory cell, enabling accurate resistance detection despite the presence of parallel current paths.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements a feedback mechanism where the detected resistance values of memory cells are used to calculate and compensate for sneak currents in subsequent readings. The system continuously updates its understanding of the memory cell states and uses this information to adjust the sneak current compensation, improving detection accuracy over time.

Inventive Principle:
Principle #23Feedback

2Reliability

If conventional forming methods are used in crosspoint memory devices, then the forming process can be performed, but the sneak current causes instability and prevents reliable forming operation

Engineering Contradiction:
Improveforming stabilityVSAvoidsneak current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the sneak current component from the total current measurement during forming operations. By calculating the expected sneak current based on the resistance values of non-selected memory cells and subtracting it from the measured current, the system obtains an accurate representation of the current through the selected memory cell, enabling reliable forming control.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses feedback from resistance measurements to dynamically adjust the forming process. The detected resistance values are used to calculate sneak currents, which are then compensated for in real-time during forming operations, creating a closed-loop control system that ensures stable and reliable forming despite the presence of parallel current paths.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If the resistance value of memory cells is not accurately detected due to sneak current, then data reading becomes unreliable, but increasing measurement precision requires complex compensation mechanisms

Engineering Contradiction:
Improveresistance detection accuracyVSAvoidcompensation circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a universal compensation approach that handles both reading and forming operations through a single sneak current compensation mechanism. The same principle of calculating and subtracting sneak current based on resistance values applies to both operations, reducing the need for separate complex compensation circuits for different functions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables stable forming and data writing/reading by accurately determining the resistance state of selected memory cells, reducing the impact of sneak currents and improving the overall performance of the memory device.

Implementation Method 1

The variable resistance memory element has a resistance value that changes according to electrical signal. The changed resistance value is kept even after turning the electrical signal off (in other words, kept in a nonvolatile manner).

Methodology Applied
Scientific EffectVariable resistance effect: Electrical Resistance

Implementation Method 2

When the reading voltage is applied, a current flows in the target memory cell to be detected (target to be read), but a current also flows via the other memory cells (memory cells other than the target memory cell) connected in parallel to the target memory cell along upper and lower lines, namely, a bit line and a word line.

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9053787B2Crosspoint nonvolatile memory device and method of driving the same
Publication Date: 2015.06.09 PANASONIC SEMICON SOLUTIONS CO LTD
  • US9053787B2 patent drawing
  • US9053787B2 patent drawing
  • US9053787B2 patent drawing

AI summary

The nonvolatile memory device includes a control circuit that controls a sense amplification circuit and a writing circuit. The control circuit changes a value of at least one of (a) a load current and (b) a forming pulse current or a forming pulse voltage, according to a total number of sneak current paths formed by memory cells each including a variable resistance element in a second resistance state having a low resistance value except a selected memory cell in a memory cell array.