Cross-Point Memory Read Circuit for Snapback Current Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for reading programmable resistance memory cells in cross-point arrays suffer from snapback currents that can change the state of programmable resistance memory elements during the reading process, leading to miss-reads and undesired state changes.
Innovation Solution
Implementing a memory system with control circuitry that provides capacitive isolation and a discharge path to prevent snapback currents from flipping the state of memory cells, using techniques like globally referenced reads and self-referenced reads with capacitive isolation and discharge paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a current is driven to a selected memory cell to read its state, then the memory cell state can be sensed, but snapback current flows through the programmable resistance memory element causing unintended state changes and miss-reads
Solution Approach 1:
A capacitor is introduced as an intermediary element between the current source and the selected memory cell. This capacitor acts as a charge reservoir that decouples the snapback current transient from the memory cell, allowing the read current to charge the capacitor without causing harmful current spikes through the memory element. The capacitor charges to the threshold voltage needed to turn on the threshold switching selector without directly driving snapback current through the programmable resistance memory element.
Solution Approach 2:
The capacitor is pre-charged to a voltage level that will subsequently turn on the threshold switching selector. This preliminary charging action prepares the circuit state before the actual read operation begins, so that when the read current is applied, the capacitor can immediately supply the necessary charge to activate the selector without causing harmful current transients through the memory cell.
2Measurement precision
If the capacitance of control circuitry is increased to improve signal-to-noise ratio, then reading accuracy improves, but snapback current magnitude increases causing more severe state changes
Solution Approach 1:
The capacitor serves as a mediator that allows the control circuitry capacitance to be increased for improved signal-to-noise ratio and reading accuracy, while simultaneously preventing this increased capacitance from directly causing proportionally larger snapback currents. The capacitor decouples the relationship between control circuitry capacitance and snapback current magnitude by providing a charge reservoir that can be charged without directly driving current through the memory element.
3Measurement precision
If read current is increased to improve signal detection, then sensing capability improves, but the voltage across the memory cell increases causing threshold switching selector to turn on and snapback current to flow
Solution Approach 1:
The capacitor acts as an intermediary that allows increased read current to be applied for improved signal detection while preventing this increased current from directly causing proportional increases in voltage across and snapback current through the memory cell. The capacitor absorbs the voltage swing, allowing the read current to charge the capacitor rather than directly increasing the voltage across the memory element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the signal-to-noise ratio and prevents unintended state changes during reading, ensuring accurate data retrieval from programmable resistance memory cells.
Implementation Method 1
temporarily provides capacitive isolation of the selected memory cell from this circuit capacitance
Data Source
AI summary
Technology for reading memory cells in a cross-point memory array. Each memory cell may have a threshold switching selector in series with a programmable resistance memory element. The memory system has control circuitry adjacent to the cross-bar memory array that is used to generate and deliver currents to the cross-bar memory array. The memory system temporarily provides capacitive isolation of the selected memory cell from capacitance of the adjacent circuitry while the snapback current is present. The memory system provides a discharge path to a node between the control circuitry and the selected memory cell during a period in which the capacitive isolation is removed.