Crosspoint Switching Architecture for Scalable Terabit Routing

The patent segments the monolithic shared memory into multiple distributed memory modules, each handling specific port pairs. This segmentation allows parallel memory operations to occur simultaneously across multiple modules, increasing overall switch capacity while maintaining the ability to perform simultaneous reads and writes from all ports.

The patent implements local quality by providing buffers only for specific input-output port pairs that require them, rather than universal buffering for all N2 combinations. This selective buffering approach reduces the total number of buffers needed while maintaining adequate bandwidth for high-traffic port pairs, thereby increasing switch capacity.

The patent enables self-service by allowing crosspoints to autonomously make routing decisions based on pre-computed scheduling information from distributed schedulers. This eliminates the need for complex centralized arbitration algorithms, as each crosspoint independently executes simple lookup and forwarding operations, maintaining scalability while reducing scheduling complexity.

The patent merges multiple distributed switch devices into a unified logical switching fabric through synchronized operation. By combining the scheduling functions and memory resources of multiple devices while maintaining independent physical implementations, the system achieves high capacity scaling without proportionally increasing flow control complexity, as the distributed architecture naturally handles timing constraints.