Crosstalk Delay Correction via Cell Drive Strength Adjustment
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Solution Overview
Problem
Current methods for correcting signal integrity crosstalk violations in integrated circuits often introduce additional violations due to the lack of systematic solutions for mitigating timing changes and the need for re-routing and buffer insertion, which can lead to logic and delay faults.
Innovation Solution
A system and method that utilize a standard cell library with multiple cell drives of the same physical size, employing a mathematical formula to incrementally increase drive strength and swap cells to correct crosstalk-induced delays without re-routing, using threshold values to identify and address timing failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cells are upsized to correct crosstalk violations, then drive strength increases and timing is improved, but cell placement is perturbed and additional crosstalk violations are introduced
Solution Approach 1:
The patent applies local quality by providing different cell drive strengths (1×, 2×, 4×, 8×, 16×) at the same physical location without changing cell placement. This allows selective upsizing of specific cells to correct crosstalk violations while maintaining the same physical layout, thereby avoiding the introduction of new violations through placement perturbations.
Solution Approach 2:
The patent changes the drive strength parameter of cells through library selection rather than physical modification. By swapping to cells with higher drive strength from the standard cell library (same physical size), the timing is improved without altering cell placement or routing, thus avoiding additional crosstalk violations.
2Reliability
If re-routing is performed to mitigate crosstalk, then signal integrity is improved, but additional crosstalk violations are introduced and design complexity increases
Solution Approach 1:
The patent resolves crosstalk violations by changing the drive strength parameter of existing cells rather than re-routing connections. This parameter-based approach maintains the original routing topology, avoiding the introduction of new violations and reducing design complexity while still achieving timing closure.
3Loss of time
If buffer insertion is used to correct timing failures, then delay is compensated, but additional violations are introduced and manufacturing complexity increases
Solution Approach 1:
The patent provides multiple drive strength options (1×, 2×, 4×, 8×, 16×) for standard cell library cells, allowing selective upsizing to compensate for crosstalk-induced delay. This local parameter adjustment eliminates the need for buffer insertion, thereby avoiding additional violations and manufacturing complexity associated with inserting extra components.
Data Source
AI summary
A system and method for repairing crosstalk delays are disclosed herein. By modeling the change in effective capacitance, one may determine the delay attributable to crosstalk, and upsize cells in the failing net according to a mathematical formula in order to counter the delay.