Hierarchical Crosstalk Noise Verification in Semiconductor Circuit Design
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Solution Overview
Problem
Current methods for crosstalk noise checking in semiconductor integrated circuits face challenges such as increased data size and reduced calculation speed as the number of layers increases, inefficient layout designs due to the need for expanded layers, and incorrect noise checking due to unaccounted wire lines passing above or adjacent to boundaries in hierarchical layers.
Innovation Solution
A design assisting apparatus that stores routing information for wire lines likely to be aggressor or victim nets across multiple layers, allowing for efficient identification and calculation of crosstalk noise without expanding all layers, using a processor to perform wire line identification and verification, thereby reducing memory usage and improving calculation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all layers are expanded with the layout of the entire semiconductor circuit completed to perform crosstalk noise check on all wire lines, then the crosstalk noise check can be performed comprehensively, but the data size greatly increases and memory is occupied, reducing calculation speed
Solution Approach 1:
The patent divides the hierarchical semiconductor circuit into multiple layers (first layer with first modules, second layer with second modules) and performs crosstalk noise checks separately for each layer. The checking apparatus processes each layer independently, maintaining comprehensive noise verification while avoiding the need to expand all layers simultaneously, thus reducing data size and improving calculation speed.
2Productivity
If the layout of a block at a layer level is completed to perform crosstalk noise check, then the noise check can be performed on that layer, but the layout of blocks may remain pending in the layer design, making it difficult to check crosstalk noise correctly
Solution Approach 1:
The patent implements a dynamic crosstalk noise checking approach where the checking apparatus can process layers based on their completion status. When a layer's layout is completed, the apparatus performs noise checks on that layer; when layouts are pending, the apparatus waits or uses available routing information. This dynamic processing allows efficient utilization of completed design portions while maintaining accurate noise verification.
3Object-affected harmful factors
If wire line spacing is widened or ground wire lines are interposed to prevent crosstalk noise, then crosstalk noise is reduced, but dead space is introduced and die size increases
Solution Approach 1:
The patent replaces physical layout modifications (widening spacing, adding ground wires) with a computational approach. The checking apparatus uses routing information stored in memory to identify and calculate crosstalk noise between wire lines, eliminating the need for physical design changes. This substitution allows noise verification without introducing dead space or increasing die size.
Data Source
AI summary
A design assisting apparatus includes a memory configured to store routing information representing first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the first wire line likely to become either one of an aggressor net and a victim net in a crosstalk noise check performed on wire lines of a module belonging to a second layer hierarchically higher than the first layer, and a processor configured to perform a wire line identifying operation identifying second wire line within the module belonging to the second layer, and likely to become either one of an aggressor net and a victim net in the crosstalk noise check performed on the first wire line represented by the routing information stored on the memory.