Crown Capacitor Fabrication via Template Layer Intermediary

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Solution Overview

Problem

In advanced DRAM manufacturing, crown capacitors face issues such as damage to lower electrodes during etching, loss of electrode material leading to decreased capacitance, and short circuits due to sidewall bowing, which hinder integration density and capacitance.

Innovation Solution

A process involving a substrate with a template layer and a patterned support layer, where holes are formed with sidewall bowing controlled by a sacrifice layer, allowing for conformal conductive layer division into lower electrodes without etching the support layer, thereby maintaining electrode integrity and increasing capacitance while preventing short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the support layer is etched to divide the conductive layer into lower electrodes, then the lower electrodes are formed, but the lower electrodes are easily damaged and capacitance decreases

Engineering Contradiction:

Improveease of forming lower electrodesVSAvoidintegrity of lower electrodes

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces a template layer as an intermediary structure between the support layer and the conductive layer. The template layer with pre-formed holes serves as a mask during etching, allowing the conductive layer to be divided into lower electrodes without directly etching the support layer, thus preventing electrode damage while achieving the desired structure

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The template layer is prepared in advance with holes formed at specific positions and depths. This preliminary action enables the subsequent etching process to proceed without damaging the lower electrodes, as the template layer protects them during the formation process

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the hole size is increased to prevent short circuits due to sidewall bowing, then the risk of short circuits decreases, but the integration density decreases

Engineering Contradiction:

Improveprevention of short circuitsVSAvoidintegration density

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies different structural characteristics to different regions: the template layer has straight sidewalls in the critical region where lower electrodes form, preventing bowing-induced short circuits, while the overall hole spacing can be minimized to maintain high integration density. This localized structural optimization resolves the contradiction between reliability and productivity

Inventive Principle:

Principle #3Local quality

3Manufacturing precision

If the etching depth is increased to form proper lower electrodes, then the electrode structure is improved, but the lower electrodes are more easily damaged

Engineering Contradiction:

Improveelectrode structure precisionVSAvoiddamage resistance of lower electrodes

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The template layer acts as a protective intermediary during deep etching. It allows the etch process to reach the required depth for proper electrode formation while protecting the lower electrodes from damage, as the template layer absorbs the mechanical stress and prevents direct contact between the etching process and the fragile electrodes

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The process effectively prevents damage to lower electrodes, maintains capacitance, and reduces the risk of short circuits, enabling higher integration density and capacitance without increasing hole size, thus improving DRAM performance.

Implementation Method 1

a substantially conformal conductive layer is formed over the substrate, and the conductive layer is divided into a plurality of lower electrodes of the crown capacitors

Methodology Applied

Scientific EffectConformal deposition: Deposition (physical)

Implementation Method 2

the support layer 106 and the template layer 104 are etched anisotropically using the photoresist layer 108 as a mask to form, in the template layer 104, holes 110

Methodology Applied

Scientific EffectAnisotropic etching:

Data Source

PatentUS7951668B2Process for fabricating crown capacitors of dram and capacitor structure

Publication Date: 2011.05.31 POWERCHIP SEMICON MFG CORP

AI summary

A process for fabricating crown capacitors is described. A substrate having a template layer thereon is provided. A patterned support layer is formed over the template layer. A sacrifice layer is formed over the substrate covering the patterned support layer. Holes are formed through the sacrifice layer, the patterned support layer and the template layer, wherein the patterned support layer is located at a depth at which bowing of the sidewalls of the holes occurs and is bowed less than the sacrifice layer at the sidewalls. A substantially conformal conductive layer is formed over the substrate. The conductive layer is then divided into lower electrodes of the crown capacitors.