Cryogenic Dielectric Plasma Etching for High-Aspect-Ratio Profiles

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Solution Overview

Problem

Current methods for high aspect ratio etching of dielectrics in semiconductor devices face challenges in achieving high etch selectivity, low sidewall etching, and maintaining straight profiles, particularly at cryogenic temperatures, where the etching of silicon dioxide and nitride layers requires different chemistries and conditions compared to silicon.

Innovation Solution

A method involving the use of cryogenic temperatures to suppress chemical etching, employing leaner fluorocarbon or fluorohydrocarbon chemistries, and incorporating gases like CF4, CHF3, and BCl3 to selectively etch dielectric layers with reduced sidewall protection, allowing for higher etch rates and improved selectivity without the need for strong sidewall passivation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional etching chemistries are used for high aspect ratio dielectric etching, then etch rate can be maintained, but sidewall etching increases and selectivity to mask decreases

Engineering Contradiction:
Improveetch rateVSAvoidsidewall profile control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent changes the temperature parameter to cryogenic conditions (below -20°C) and modifies the chemistry composition by using leaner fluorocarbon or fluorohydrocarbon chemistries with specific gases (CF4, CHF3, BCl3). This parameter change suppresses chemical etching and sidewall deposition, enabling high etch rates while maintaining straight sidewall profiles and high selectivity to the mask pattern.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies different conditions to different regions: the etch front experiences high ion flux and reactive species for rapid vertical etching, while the sidewalls experience suppressed chemical reactions due to cryogenic temperature, resulting in minimal lateral etching and straight profiles. This local differentiation of etching behavior resolves the contradiction between etch rate and sidewall control.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If strong sidewall passivation is used to protect sidewalls during etching, then sidewall profile is maintained, but etch rate decreases

Engineering Contradiction:
Improvesidewall profileVSAvoidetch rate
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

By changing the temperature to cryogenic conditions and using leaner chemistries, the patent suppresses the formation of protective polymer films on sidewalls. This eliminates the need for strong sidewall passivation while maintaining straight sidewall profiles, thereby removing the trade-off between sidewall protection and etch rate.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent converts the typically harmful effect of chemical etching and sidewall deposition into a benefit by using cryogenic temperature to suppress these reactions. This suppression prevents sidewall bowing and tapering while allowing high etch rates, effectively turning what would normally require strong passivation into a condition where passivation is unnecessary.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Manufacturing precision

If silicon-containing masks are used for high aspect ratio etching, then selectivity and profile control are improved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improveetch selectivity and profile controlVSAvoidmask structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the etching parameters (temperature and chemistry) to cryogenic conditions with leaner fluorocarbon/fluorohydrocarbon chemistries, which provide inherently high selectivity to the mask and suppressed sidewall etching. This eliminates the need for complex silicon-containing mask structures, allowing the use of simpler amorphous carbon masks while maintaining high aspect ratio etching quality.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts the silicon component from the mask structure, replacing complex silicon-containing masks with simpler amorphous carbon masks. The cryogenic etching chemistry provides the necessary selectivity and profile control without requiring silicon in the mask, thereby reducing manufacturing complexity and cost.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables efficient etching of high aspect ratio dielectric structures with enhanced selectivity and reduced lateral etching, breaking the trade-off between etch rate and sidewall profile, and allows for the use of amorphous carbon masks without the need for silicon-containing masks, thereby reducing costs and defects.

Implementation Method 1

The stack is cooled with a coolant with a coolant temperature below -20° C.

Methodology Applied
Scientific EffectCryogenic cooling: Cryogenics

Implementation Method 2

An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas.

Methodology Applied
Scientific EffectPlasma generation: Plasma

Data Source

PatentUS20240258127A1Plasma etching chemistries of high aspect ratio features in dielectrics
Publication Date: 2024.08.01 LAM RES CORP
  • US20240258127A1 patent drawing
  • US20240258127A1 patent drawing
  • US20240258127A1 patent drawing

AI summary

A method for etching features in a stack below a patterned mask in an etch chamber is provided. The stack is cooled with a coolant with a coolant temperature below −20° C. An etch gas is flowed into the etch chamber. A plasma is generated from the etch gas. Features are selectively etched into the stack with respect to the patterned mask.