Cryogenic Multilayer Interconnect Structure for CTE-Matched Heat Dissipation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Cryogenic electronic systems face challenges in designing and fabricating multilayer interconnect structures due to material mismatches in coefficient of thermal expansion (CTE) and reduced thermal conductivity at deep cryogenic temperatures, leading to mechanical stresses and heat dissipation issues.

Innovation Solution

A cryogenic multilayer interconnect structure using a molybdenum substrate with copper cladding layers, matched CTE, and high thermal conductivity, incorporating niobium superconducting layers and polymer dielectric layers, to minimize mechanical stresses and enhance heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional materials are used in interconnect structures at deep cryogenic temperatures, then material availability and ease of manufacture are improved, but thermal conductivity decreases and mechanical stresses increase due to CTE mismatch

Engineering Contradiction:
Improveease of manufactureVSAvoidreliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent employs a composite interconnect structure consisting of a copper substrate layer combined with a dielectric layer containing embedded conductors. The copper substrate provides high thermal conductivity at cryogenic temperatures, while the dielectric layer with embedded conductors provides electrical interconnect functionality. This composite approach allows the structure to simultaneously achieve excellent thermal management and reliable electrical performance in cryogenic environments, resolving the contradiction between ease of manufacture and reliability.

Inventive Principle:
Principle #40Composite materials

2Adaptability or versatility

If materials with different CTE are used to provide functional layers, then functional performance is improved, but mechanical stresses increase due to CTE mismatch

Engineering Contradiction:
Improvefunctional performanceVSAvoidmechanical stresses
Core Design Contradiction:
Adaptability or versatilityVSStress or pressure

Solution Approach 1:

The patent applies local quality by using a copper substrate layer specifically optimized for thermal conductivity in regions requiring heat dissipation, while employing a dielectric layer with embedded conductors in regions requiring electrical interconnect functionality. This localized material selection allows each layer to perform its specific function optimally while the overall structure manages thermal and mechanical stresses through the copper substrate's high ductility and thermal properties.

Inventive Principle:
Principle #3Local quality

3Temperature

If heat dissipation is enhanced in interconnect structures, then thermal management is improved, but material selection becomes more constrained due to CTE matching requirements

Engineering Contradiction:
Improvethermal conductivityVSAvoiddevice complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The copper substrate layer serves multiple functions simultaneously: it provides the primary thermal conduction path for heat dissipation, acts as a mechanical support structure due to its high ductility, and serves as a foundation for the dielectric layer with embedded conductors. This multi-functionality reduces device complexity by eliminating the need for separate thermal management and structural support components, while the copper's CTE characteristics help match with cryogenic electronics components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The structure provides a good match in CTE with cryogenic chips, reducing mechanical stresses and significantly increasing thermal conductivity, ensuring reliable operation and efficient heat dissipation in cryogenic environments.

Implementation Method 1

The interconnect structure also provides heat dissipation for components attached to this structure... most materials experience a reduction in thermal conductivity as a function of temperature... significantly increasing thermal conductivity

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

Superconducting materials are typically utilized for forming the conductive layers to reduce the joule heating generated in the conductive layers

Methodology Applied
Scientific EffectSuperconductivity: Superconductivity

Implementation Method 3

Differences in the coefficient of thermal expansion (CTE) of different materials utilized in the interconnect structure may further limit suitable materials since such differences can result in mechanical stresses in the structure as temperature changes... good match in CTE with cryogenic chips, reducing mechanical stresses

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentEP4327373B1Multilayer superconducting structures for cryogenic electronics
Publication Date: 2025.11.12 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP4327373B1 patent drawingFigure 1
  • EP4327373B1 patent drawingFigure 2A~2B
  • EP4327373B1 patent drawingFigure 3

AI summary

A cryogenic multilayer interconnect structure has a substrate including a molybdenum layer, a first insulating layer on the substrate and a first superconducting layer on the first insulating layer. The molybdenum layer has a coefficient of thermal expansion (CTE) that is well matched with the CTE of cryogenic electronic chips that are to be attached to the cryogenic multilayer interconnect structure. The substrate may be a copper clad molybdenum substrate that provide the CTE advantages provided by the molybdenum layer while also providing an increased thermal conductivity to improve the dissipation of heat generated by cryogenic electronic chips coupled to the substrate.