Cryogenic Recess Etching with Sidewall Protection and High Etch Rate

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Solution Overview

Problem

The challenge in semiconductor manufacturing is effectively etching recess portions while protecting the side walls from bowing and maintaining high etching rates, particularly when using cryogenic etching methods.

Innovation Solution

A method involving the formation of a surface layer using a halogen-free gas on the processing target object, followed by etching with a halogen-containing gas, while alternating between applying and not applying a high-frequency voltage, and controlling temperature and pressure to enhance protection and etching efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If cryogenic etching is used to maintain side wall protection, then side wall bowing is prevented, but etching rate decreases

Engineering Contradiction:
Improveside wall protectionVSAvoidetching rate
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The etching process is divided into multiple alternating cycles: a first etching step using CF4 gas at room temperature to etch the silicon oxide film, followed by a second etching step using NF3 gas at cryogenic temperature to etch the silicon nitride film and protect side walls. This segmentation allows each step to optimize for its specific function, resolving the contradiction between etching rate and side wall protection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs periodic alternation between room temperature and cryogenic temperature etching steps. The temperature and gas type are switched in cycles, with the room temperature step providing high etching rate and the cryogenic step providing side wall protection. This periodic action enables the system to achieve both high productivity and manufacturing precision over the complete cycle.

Inventive Principle:
Principle #19Periodic action

2Productivity

If halogen-containing gas is used for etching, then etching rate increases, but side wall protection deteriorates

Engineering Contradiction:
Improveetching rateVSAvoidside wall protection
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Different halogen-containing gases are segmented into separate etching steps: CF4 gas is used in the first step for high-rate etching of silicon oxide, while NF3 gas is used in the second step for etching silicon nitride with side wall protection. Each gas is optimized for its specific material and function, allowing both high etching rate and side wall protection to be achieved through proper segmentation of the etching process.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves etching rates by preventing side wall bowing and maintaining film integrity, allowing for precise control of etching processes and efficient formation of semiconductor structures.

Implementation Method 1

forming a surface layer on a recess portion of a processing target object by supplying a first gas onto the processing target object while cooling the processing target object and without applying a high-frequency voltage to a processing chamber

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Implementation Method 2

etching the processing target object by supplying a second gas onto the processing target object while applying the high-frequency voltage to the processing chamber, wherein the second gas contains a halogen

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 3

forming a surface layer on a recess portion of a processing target object by supplying a first gas onto the processing target object while cooling the processing target object

Methodology Applied
Scientific EffectCondensation: Condensation

Data Source

PatentUS20250385108A1Method of manufacturing semiconductor device
Publication Date: 2025.12.18 KIOXIA CORP
  • US20250385108A1 patent drawing
  • US20250385108A1 patent drawing
  • US20250385108A1 patent drawing

AI summary

According to one embodiment, a method of manufacturing a semiconductor device using a semiconductor manufacturing apparatus, includes: forming a surface layer on a recess portion of a processing target object, by supplying a first gas onto the processing target object while cooling the processing target object and without applying a high-frequency voltage to a processing chamber of the semiconductor manufacturing apparatus, wherein the first gas contains no halogens; and etching the processing target object by supplying a second gas onto the processing target object while applying the high-frequency voltage to the processing chamber, wherein the second gas contains a halogen.