Cryogenic Implantation for Epitaxial SiGe Lattice Integrity
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Solution Overview
Problem
Conventional semiconductor implantation processes, such as pre-amorphization implant (PAI), often result in collateral damage to the lattice of target materials, leading to dislocation flaws and stress relaxation in epitaxial materials, which can cause low junction leakage and reliability issues.
Innovation Solution
A novel semiconductor process involving a cryogenic procedure below −30°C for at least one implanting step, including pre-amorphization and source/drain implanting, to prevent dislocation flaws in epitaxial materials, using a substrate with a recess and an embedded semiconductive epitaxial layer, and incorporating a stress memory layer to enhance device speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pre-amorphization implant (PAI) is performed to form amorphous region, then amorphization is enhanced, but dislocation flaws are formed in the lattice
Solution Approach 1:
The patent applies parameter changes by performing the pre-amorphization implant at cryogenic temperature (below -30°C, preferably below -100°C). This temperature parameter change fundamentally alters the material behavior during implantation, allowing enhanced amorphization while preventing dislocation formation through reduced atomic mobility and different defect dynamics at low temperature.
2Manufacturing precision
If pre-amorphization implant (PAI) is performed to form amorphous region, then amorphization is enhanced, but stress relaxation occurs in epitaxial material
Solution Approach 1:
The patent utilizes parameter changes by conducting the implantation process at cryogenic temperature (below -30°C). This temperature parameter prevents stress relaxation by maintaining the epitaxial material in a rigid, low-mobility state during and after implantation, thereby preserving the stress state in the strained-layer structure while still achieving the desired amorphization.
3Ease of manufacture
If conventional implantation is performed at room temperature, then implantation process is simple, but dislocation flaws and residual damage occur
Solution Approach 1:
The patent applies parameter changes by implementing the implantation process at cryogenic temperature (below -30°C, preferably below -100°C). While this adds temperature control requirements, it dramatically improves material integrity by preventing dislocation formation and reducing residual damage, thereby achieving better device performance and reliability.
Solution Approach 2:
The patent exploits phase transitions by utilizing the cryogenic temperature regime to change the physical state and behavior of the epitaxial material during implantation. The material exists in a different thermal phase at below -30°C compared to room temperature, which fundamentally alters how damage accumulates and how the material responds to ion bombardment, preventing dislocation formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The cryogenic process effectively prevents dislocation flaws and stress relaxation, improving the reliability and performance of semiconductor devices by reducing residual damage and enhancing epitaxial material integrity.
Implementation Method 1
a novel semiconductor implantation process is still needed to prevent the epitaxial material form dislocation flaws after the pre-amorphization implanting step
Implementation Method 2
The present invention proposes multiple possible novel semiconductor processes. The novel semiconductor processes of the present invention include at least one implanting step carried out in a cryogenic procedure below −30° C.
Implementation Method 3
a pre-amorphization implant (PAI) procedure is carried out on the embedded semiconductive epitaxial layer to form an amorphous region
Implementation Method 4
this enhancing amorphization technique enhances the amorphization by implantation to later reduce the residual damage post-anneal
Implementation Method 5
a source/drain implanting procedure is carried out on the embedded semiconductive epitaxial layer to form a source doping region and a drain doping region
Implementation Method 6
a source/drain annealing procedure is carried out to form at the source and drain in the substrate
Implementation Method 7
a source/drain annealing procedure is carried out to form at the source and drain in the substrate
Data Source
AI summary
First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.