Cryogenic Chip-on-Chip TSV Assembly for Low-Parasitic Interconnects

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Solution Overview

Problem

Existing cryogenic quantum computing systems face challenges in maintaining low resistance conductor wires for efficient power delivery and signal integrity at cryogenic temperatures due to parasitic capacitance and resistance issues in conductor materials.

Innovation Solution

The implementation of through substrate vias (TSVs) made of solid core conductive materials, such as copper, directly connected to a silicon substrate without an insulating shell, along with a backside redistribution layer (RDL) to reduce parasitic capacitance and provide low resistance paths for control circuits in hybrid electronic/photonic packages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional conductor materials and structures are used in cryogenic quantum computing systems, then the system can be manufactured with standard processes, but the resistance and parasitic capacitance increase leading to poor power delivery and signal integrity

Engineering Contradiction:

Improvepower delivery and signal integrityVSAvoidconductor structure complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent removes the insulating shell typically surrounding conductor wires, extracting only the essential conductive function. This exposes the copper core directly to the silicon substrate, eliminating the insulating layer that causes parasitic capacitance while maintaining electrical conductivity. The conductor is reduced to its fundamental conductive element without unnecessary insulating encapsulation.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs asymmetric conductor geometry by using non-circular cross-sections (such as rectangular or elliptical profiles) for the through-substrate vias. This asymmetric shape optimizes the electrical field distribution and reduces parasitic capacitance compared to conventional symmetric circular conductors, while still maintaining effective power delivery and signal transmission at cryogenic temperatures.

Inventive Principle:

Principle #4Asymmetry

2Object-affected harmful factors

If solid core conductive materials without insulating shells are used, then parasitic capacitance is reduced, but manufacturing precision requirements increase

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidvia formation accuracy

Core Design Contradiction:

Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The patent performs preliminary actions by pre-forming the through-substrate vias with precise dimensions and positions before final conductor material deposition. The via structures are prepared in advance with controlled depth, diameter, and alignment, ensuring that when the solid core conductive material is inserted, the manufacturing precision requirements are already satisfied. This preliminary structuring reduces the complexity of achieving high precision in the final assembly.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If through substrate vias with solid core conductors are implemented, then resistance is reduced for better power delivery, but device complexity increases

Engineering Contradiction:

ImproveresistanceVSAvoidhybrid package structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple functions into the through-substrate via structure. The same via serves as the mechanical support structure, the electrical conductor for power delivery, and the thermal path for heat management. By combining these functions into a single integrated element rather than separate components, the device complexity is reduced despite the advanced functionality achieved. The hybrid electronic/photonic package benefits from this consolidation.

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly reduces resistance and parasitic capacitance, ensuring robust power delivery and signal integrity at cryogenic temperatures, enhancing the performance of cryogenic quantum computing systems.

Implementation Method 1

through substrate vias used in such assemblies and methods of forming thereof... electrically conductive through substrate vias... significantly reduces resistance and parasitic capacitance, ensuring robust power delivery and signal integrity at cryogenic temperatures

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

at least one of a cavity and an underfill material having a lower thermal conductivity than materials of the photonic die and the electronic die is located between the photonic die and the electronic die

Methodology Applied

Scientific EffectThermal insulation: Thermal Insulation

Data Source

PatentUS20260096427A1Cryogenic chip-on-chip assemblies with through substrate vias and methods of forming thereof

Publication Date: 2026.04.02 PSIQUANTUM CORP

AI summary

A device includes a photonic cryo die containing photonic components, and an electronic die bonded to the photonic die, the electronic die containing electrically conductive through substrate vias. The electrically conductive through silicon vias can electrically connect a backside redistribution layer to control circuitry for operation in a cryogenic environment in a compact package that exhibits low resistance and low parasitic capacitance.