Low Cost Cryptographic Accelerator for Microcontrollers

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Solution Overview

Problem

Microcontrollers used in secure communications face performance limitations due to the high cost of implementing cryptographic algorithms like AES and SHA2, which are typically slow when implemented in software and prohibitively expensive to support in hardware for small MCUs.

Innovation Solution

A hardware-software combination approach using a central processing unit (CPU) to move data to a hardware accelerator for processing, allowing for efficient execution of cryptographic operations with minimal hardware cost, enabling support for cryptographic algorithms on low-cost MCUs by optimizing the CPU execution and sharing logic and registers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If cryptographic algorithms are implemented in software, then hardware cost is reduced, but execution speed becomes very slow

Engineering Contradiction:

Improvehardware costVSAvoidexecution speed

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The cryptographic processing system is segmented into two parts: a hardware accelerator that performs specific cryptographic operations (AES, SHA2, GCM) and a software controller (CPU) that manages data flow and algorithm coordination. This segmentation allows the hardware to handle computationally intensive operations while the software handles control logic, resolving the contradiction between low hardware cost and high execution speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A hardware accelerator acts as an intermediary component between the CPU and cryptographic algorithms. The accelerator receives data from the CPU, performs cryptographic transformations in hardware, and returns results to the CPU. This intermediary hardware component enables fast cryptographic processing without requiring the entire system to be hardware-based, thus maintaining cost-effectiveness while improving speed.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If cryptographic algorithms are implemented in hardware, then execution speed is improved, but hardware cost becomes prohibitive for small MCUs

Engineering Contradiction:

Improveexecution speedVSAvoidhardware cost

Core Design Contradiction:

ProductivityVSEase of manufacture

Solution Approach 1:

Instead of providing full cryptographic functionality across all MCUs, the hardware accelerator provides localized quality enhancement by implementing only the most critical cryptographic operations (AES encryption/decryption, SHA2 hashing, and GCM authentication). This selective hardware implementation delivers speed improvements where most needed while keeping the hardware footprint and cost acceptable for small MCUs.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The hardware accelerator implements partial cryptographic functionality rather than complete standalone cryptographic processors. By providing accelerated routines for specific algorithms and operations rather than full cryptographic suites, the system achieves sufficient speed improvement for security-critical operations without incurring the prohibitive costs of complete hardware cryptographic solutions.

Inventive Principle:

Principle #16Partial or excessive action

3Productivity

If dedicated hardware modules are designed for standalone crypto operations, then cryptographic performance is maximized, but device complexity and cost increase

Engineering Contradiction:

Improvecryptographic performanceVSAvoidhardware architecture

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The hardware accelerator is designed as a universal cryptographic processing unit that can perform multiple cryptographic functions (AES in various modes, SHA2 family hashes, GCM authentication) through a single integrated architecture. This multi-functional design eliminates the need for separate dedicated hardware modules for each cryptographic algorithm, reducing device complexity while maintaining high cryptographic performance across multiple standards.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Multiple cryptographic functions are merged into a single hardware accelerator module that shares common resources such as data paths, registers, and control logic. The accelerator combines AES encryption/decryption, SHA2 hashing, and GCM authentication capabilities in one unified hardware block, simplifying the overall device architecture compared to having separate dedicated modules for each cryptographic operation.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11841981B2Low cost cryptographic accelerator

Publication Date: 2023.12.12 ATMEL CORP

AI summary

A low-cost cryptographic accelerator is disclosed that accelerates inner loops of a cryptographic process. The cryptographic accelerator performs operations on cryptographic data provided by a central processing unit (CPU) running a software cryptographic process to create a combined hardware and software cryptographic process, resulting in a lower cost secure communication solution than software-only or hardware-only cryptographic processes. In an embodiment, a cryptographic accelerator comprises: an interface configured to receive cryptographic data, the cryptographic data indicating a particular cryptographic process to be performed on the cryptographic data; transformation logic configured to perform a cryptographic operation on the cryptographic data according to the cryptographic process, the transformation logic including logic for performing cryptographic operations for a plurality of different cryptographic processes; and a state register configured for storing a result of the cryptographic operation.