Cryptographic Hardware Accelerator Dummy Addressing Side-Channel Protection
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Solution Overview
Problem
Cryptographic hardware accelerators using elliptic curve cryptography are vulnerable to horizontal address-bit side-channel attacks, vertical address-bit attacks, localized electromagnetic analysis, and fault injection attacks, as existing countermeasures like regularity and atomicity principles are insufficient in masking key-dependent addressing operations.
Innovation Solution
The implementation of a cryptographic hardware accelerator that uses a controller to perform dummy-addressing operations, selecting and using pre-assigned dummy addresses in addition to the first address for block addressing, thereby camouflaging the energy consumption and control signal flow, making it difficult to determine the addressed blocks based on energy consumption or electromagnetic radiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy-addressing operations are implemented to mask key-dependent addressing, then resistance against side-channel attacks is improved, but device complexity increases
Solution Approach 1:
The patent introduces a dummy-addressing mechanism as an intermediary layer between the controller and the computational blocks. This mechanism includes dummy address generation logic and dummy addressing control circuits that mediate the addressing process, adding confusion to side-channel attacks while maintaining functional correctness through selective enabling based on control signals
2Measurement precision
If multiple dummy addresses are pre-assigned to blocks for camouflaging purposes, then measurement precision of energy consumption patterns is reduced, but address space utilization is worsened
Solution Approach 1:
The patent changes the addressing parameter by assigning multiple dummy addresses to each computational block in addition to their functional addresses. This parameter change creates multiple possible address targets for each block, thereby camouflaging the actual accessed block and reducing the precision of energy consumption pattern analysis for side-channel attacks
Data Source
AI summary
A hardware accelerator is disclosed for performing a computational operation in a cryptographic application comprises one or more addressable computational blocks and a plurality of addressable register blocks. A bus is used for data exchange between the blocks in the form of read-from-bus operations and write-to-bus operations in the course of performing the computational operation. A controller for controlling the data exchange performs a block addressing operation using a respective pre-assigned first address of the blocks for addressing the one or more of the blocks involved in a write-to-bus operation in the data exchange. The controller performs a dummy-addressing selection operation to select one or more of the blocks for a dummy addressing operation and a dummy-addressing operation of the selected one or more of the blocks for dummy-addressing the one or more of the selected blocks in the write-to-bus operation.