Cryptographic Circuit Metadata Encryption Latency

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Solution Overview

Problem

Existing memory systems face latency penalties when using Inline Memory Encryption (IME) algorithms like AES-XTS for encrypting both cache line data and metadata, which is critical for secure and efficient data processing in emerging applications like AI and ML.

Innovation Solution

Implementing a cryptographic circuit that uses different modes of AES, such as AES-XTS for cache line data and AES-CTR for metadata, allowing for parallel encryption and decryption operations, thereby reducing latency and improving energy efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If AES-XTS algorithm is used to encrypt both cache line data and metadata, then data security is improved, but decryption latency increases significantly

Engineering Contradiction:

Improvedata securityVSAvoiddecryption latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the encryption/decryption process into two separate segments: one for cache line data using AES-XTS algorithm and another for metadata using AES-CTR algorithm. This segmentation allows each part to be processed with the most appropriate algorithm, reducing overall decryption latency while maintaining security.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different cryptographic properties to different parts of the data structure. AES-XTS is applied to cache line data where strong security is paramount, while AES-CTR is applied to metadata where faster access is critical. This local optimization resolves the contradiction between security and latency.

Inventive Principle:

Principle #3Local quality

2Reliability

If AES-XTS algorithm is used for metadata encryption, then security is improved, but energy consumption increases

Engineering Contradiction:

ImprovesecurityVSAvoidenergy consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent optimizes energy consumption by applying the most energy-efficient algorithm to each data type. AES-CTR requires fewer computational resources for metadata encryption/decryption compared to AES-XTS, reducing overall energy consumption while maintaining adequate security for metadata.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the cryptographic algorithm parameter (from AES-XTS to AES-CTR) for metadata processing, which fundamentally alters the computational complexity and energy requirements of the operation, achieving lower energy consumption.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If separate encryption algorithms are used for metadata and cache line data, then processing speed is improved, but device complexity increases

Engineering Contradiction:

Improveprocessing speedVSAvoidcryptographic circuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent employs a universal cryptographic circuit capable of performing multiple functions: it can execute both AES-XTS and AES-CTR algorithms, and can process both cache line data and metadata. This multi-functionality achieves high processing speed without proportionally increasing device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250047469A1Reduced latency metadata encryption and decryption

Publication Date: 2025.02.06 RAMBUS INC

AI summary

Techniques for providing reduced latency metadata encryption and decryption are described herein. A memory buffer device having a cryptographic circuit to receive a first data and a first metadata associated with the first data. The cryptographic circuit can encrypt or decrypt the first metadata using a first cryptographic algorithm. The cryptographic circuit can encrypt or decrypt the first data using a second cryptographic algorithm. The first data and the first metadata can be stored at a same location, within a memory device, corresponding to a memory address.