Cryptographic Coprocessor Latency Reduction in Secure Automotive Systems
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Solution Overview
Problem
Current secure processing systems in automotive applications face challenges in balancing security and latency, particularly in cryptographic operations, due to the separation of secure and non-secure elements which can introduce significant latency in encryption and decryption processes, impacting real-time applications.
Innovation Solution
A processing system with a cryptographic coprocessor that includes a key storage memory and a hardware crypto engine, allowing for direct processing of data within the secure domain while minimizing latency by using separate clock signals for secure and non-secure elements, and enabling encryption and decryption operations without involving the non-secure processing unit extensively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data processing is performed in the secure domain with separate secure and non-secure elements, then security is improved, but latency increases
Solution Approach 1:
The processing system is divided into separate secure and non-secure elements with distinct processing units. The secure element handles cryptographic operations independently while the non-secure element handles application logic, allowing each to operate optimally without compromising the other. This segmentation enables security isolation while managing latency through dedicated communication channels.
Solution Approach 2:
A communication interface acts as an intermediary between the secure and non-secure elements, facilitating efficient data exchange. The interface includes buffers and control logic that optimize the transfer of data between domains, reducing the latency penalty associated with cross-domain communication while maintaining security boundaries.
2Reliability
If cryptographic operations are performed using separate secure elements, then encryption security is improved, but processing speed decreases
Solution Approach 1:
The cryptographic coprocessor merges hardware acceleration capabilities with the secure element, combining the security benefits of dedicated cryptographic processing with the performance advantages of integrated hardware. The coprocessor includes dedicated cryptographic units that work in conjunction with the secure element to provide both security and speed.
Solution Approach 2:
Software-based cryptographic operations are replaced with hardware-accelerated cryptographic processing. The cryptographic coprocessor uses dedicated hardware circuits to perform encryption and decryption operations, replacing slower software implementations with faster hardware-based operations that maintain security through the secure element's protected architecture.
3Reliability
If the secure element is isolated from the non-secure element, then key protection is improved, but system complexity increases
Solution Approach 1:
The secure element is designed with multi-functionality, handling not only cryptographic key storage but also cryptographic operations, certificate management, and secure communication functions. This universal design consolidates multiple security functions into a single element, reducing overall system complexity while maintaining strong key protection through isolation.
Data Source
AI summary
A processing system includes a first processing unit; a second processing unit; and a cryptographic coprocessor communicatively coupled to the first processing unit and the second processing unit. The cryptographic coprocessor includes a key storage memory for storing a cryptographic key; a first interface configured to receive source data to be processed directly from the first processing unit; a hardware cryptographic engine configured to process the source data as a function of the cryptographic key stored in the key storage memory; a second interface configured to receive a first cryptographic key directly from the second processing unit; and a hardware key management circuit configured to store the first cryptographic key in the key storage memory.